
RS8234
10.0 Local Processor Interface
ATM ServiceSAR Plus with xBR Traffic Management
10.3 Bus Cycle Descriptions
N8234DSC
PRELIMINARY
10-5
10.3 Bus Cycle Descriptions
Throughout the bus cycle descriptions, “cycle” refers to a single SYSCLK cycle
ending with a rising edge. An arbitration cycle is one in which the memory
requests from the local processor and internal memory consumers are compared,
and the one with the highest priority is granted the memory access on the next
cycle. A memory access that was previously arbitrated might occur on an
arbitration cycle. Once the local processor has successfully acquired the memory
controller, it holds the bus until it is relinquished by the assertion of PBLAST* on
the last data cycle. Therefore, local processor burst transfers will always be
completed, and can theoretically be of arbitrary length. However, in practice, burst
transfers should be limited to four or less. The maximum arbitration delay for a
local processor access is on the order of 20 cycles; however, it will typically be
from one to four cycles. This parameter is heavily influenced by the SYSCLK
frequency, line rate, number of VCCs, idle cell ratio, and SRAM access speed.
Therefore, a system design in which local processor accesses must occur within a
fixed time period is not recommended.
10.3.1 Single Read Cycle, Zero Wait State Example
Figure 10-2 illustrates a single read cycle with zero wait states. During the
address cycle (cycle one) at the rising edge of SYSCLK with PCS* and PAS*
active, a memory request is generated by the processor interface circuitry. Also at
this time, the read/write select, bank select, and word select inputs (PWNR,
PBSEL[1:0], and PADDR[1:0]) are internally latched. The byte enables
(PBE[3:0]*) are Don’t-Cares during reads. During cycle two, this local processor
memory request is processed by the memory arbitration circuitry. If no other
memory consumers request an access on the same cycle, the local processor is
granted access on cycle three. However, to take into account bus transceiver
turnaround, cycle three is always a wait or bus recovery state, which gives
sufficient time for the address from the processor to access the SRAM. For zero
wait state SRAM, unless a wait state is inserted by the processor, the data is
available to be latched into the processor on cycle four, which is indicated by the
assertion of PRDY*. Cycle five is an arbitration cycle for the internal memory
consumers, which might have requested access during the processor access. It
also serves as a bus recovery cycle for the processor. Once the PCS*, PAS*,
PWNR, PBSEL[1:0], and PADDR[1:0] are sampled at cycle one, they are
Don’t-Cares for the remainder of the access. DT/R* is an output supplied by the
local processor to indicate the direction of the data transceivers. The RS8234
PDAEN* signal is active to enable data and address.