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參數(shù)資料
| 型號： | 28F008C3 |
| 廠商： | Intel Corp. |
| 英文描述： | 3 VOLT ADVANCED+ BOOT BLOCK 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
| 中文描述： | 3伏高級啟動塊8 - ，16 - ，32 - Mbit閃存家庭 |
| 文件頁數(shù)： | 11/49頁 |
| 文件大?。?/td> | 408K |
| 代理商： | 28F008C3 |
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E
SMART 3 ADVANCED BOOT BLOCK
–BYTE-WIDE
11
PRELIMINARY
Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions
(Continued)
Symbol
Type
Name and Function
V
CCQ
INPUT
OUTPUT V
CC
:
Enables all outputs to be driven to 2.0V ±10% while the
V
CC
is at 2.7V. When this mode is used, the V
CC
should
be regulated to
2.7V–2.85V to achieve lowest power operation (see Section 6.1: DC
Characteristics: V
CCQ
= 1.8V–2.2V).
This input may be tied directly to V
CC
(2.7V–3.6V).
See the DC Characteristics for further details.
V
CC
DEVICE POWER SUPPLY:
2.7V–3.6V
V
PP
PROGRAM/ERASE POWER SUPPLY:
For erasing memory array
blocks or programming data in each block, a voltage of either 2.7V–3.6V
or 12V
±
5% must be applied to this pin. When V
PP
< V
PPLK
all blocks
are locked and protected against Program and Erase commands.
Applying 11.4V–12.6V to V
PP
can only be done for a maximum of 1000
cycles on the main blocks and 2500 cycles on the parameter blocks.
V
PP
may be connected to 12V for a total of 80 hours maximum (see
Section 3.4 for details).
GND
GROUND:
For all internal circuitry. All ground inputs
must
be
connected.
NC
NO CONNECT:
Pin may be driven or left floating.
2.2
Block Organization
The Smart 3 Advanced Boot Block is an
asymmetrically-blocked architecture that enables
system integration of code and data within a single
flash
device.
Each
block
independently of the others up to 10,000 times. For
the address locations of each block, see the
memory maps in Figure 4 (top boot blocking) and
Figure 5 (bottom boot blocking).
can
be
erased
2.2.1
PARAMETER BLOCKS
The Smart 3 Advanced Boot Block flash memory
architecture includes parameter blocks to facilitate
storage of frequently updated small parameters
(e.g., data that would normally be stored in an
EEPROM. By using software techniques, the byte-
rewrite functionality of EEPROMs can be emulated.
Each 8-/16-Mbit device contains eight parameter
blocks of 8 Kbytes (8,192-bytes) each.
2.2.2
MAIN BLOCKS
After the parameter blocks, the remainder of the
array is divided into equal size main blocks for data
or code storage. Each 16-Mbit device contains
thirty-one 64-Kbyte (65,536-byte) blocks. Each
8-Mbit device contains fifteen 64-Kbyte blocks.
相關PDF資料 |
PDF描述 |
|---|---|
| 28F008SA | 8-MBIT (1-MBIT x 8) FlashFileTM MEMORY |
| 28F008SA-L | 8-MBIT (1 MBIT x 8) FLASHFILETM MEMORY |
| 28F008S3 | 3 V FlashFile Memory(3V閃速存儲器) |
| 28F016S3 | 3 V FlashFile Memory(3V閃速存儲器) |
| 28F008S5 | 8-MBIT 5 VOLT FlashFile Memory(8M位5V閃速存儲器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 28F008S3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Byte-Wide Smart 3 Flashfile Memory Family 4 8 and |
| 28F008S5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BYTE-WIDE SMART 5 FlashFile MEMORY FAMILY 4. 8. AND 16 MBIT |
| 28F008SA | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:8 MBIT (1 MBIT x 8) FLASH MEMORY |
| 28F008SA-L | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:8 MBIT (1 MBIT x 8) FLASH MEMORY |
| 28F008SAT-ZW | 制造商: 功能描述: 制造商:undefined 功能描述: |
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