參數(shù)資料
型號(hào)： 28F320B3
廠商： Intel Corp.
英文描述： SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY
中文描述： 智能高級(jí)啟動(dòng)3座4 - ，8 - ，16 - ，32 - Mbit閃存家庭
文件頁(yè)數(shù)： 15/82頁(yè)
文件大小： 749K
代理商： 28F320B3
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Preliminary
9
3.0
Product Operations
3.1
Bus Operations
The 1.8 Volt Intel
Wireless Flash Memory
’
s on-chip Write State Machine (WSM) manages erase
and program algorithms. The local CPU controls the in-system read, program, and erase operations
of the flash device. Bus cycles to and from the flash device conform to standard microprocessor
bus operations. RST#, CE#, OE#, WE#, and ADV# signals control the flash. WAIT informs the
CPU of valid data during burst reads. S-OE#, S-WE#, S-CS
1
#, S-CS
2
, S-LB# and S-UB# control
the SRAM. S-UB# and S-LB# must be tied together to restrict x16 mode.
Table 3
summarizes bus
operations.
NOTES:
1. Manufacturer and device ID codes are accessed by Read ID Register command.
2. Query and status register accesses use only DQ
. All other accesses use DQ
15-0
.
3. X must be V
or V
for control signals and addresses.
4. Refer to
Table 5,
“
Command Bus Definitions
”
on page 11
for valid D
IN
during a write operation.
5. Two devices may not drive the memory bus at the same time.
6. The SRAM can be placed into data retention mode by lowering the S-V
CC
to the V
DR
limit when in standby
mode.
7. Always tie S-UB# and S-LB# together.
3.2
Flash Command Definitions
Device operations are selected by writing specific commands to the Command User Interface
(CUI).
Table 4,
“
Command Code and Descriptions
”
on page 10
lists all possible command codes
and descriptions.
Table 5,
“
Command Bus Definitions
”
on page 11
further defines command bus
cycle operations. Since commands are partition-specific, it is important to write commands within
the target partition range.
Multi-cycle command writes to the flash memory partition must be issued sequentially without
intervening command writes. For example, an Erase Setup command to partition X must be
immediately followed by the Erase Confirm command in order to be executed properly. The
address given during the Erase Confirm command determines the location of the erase. If the Erase
Table 3. Bus Operations
M
N
R
C
O
W
A
W
S
1
#
S
2
S
S
S
S
7
D
[
FLASH
Read
1,2, 5
V
IH
V
IL
V
IL
V
IH
V
IL
Valid
SRAM must be in High-Z
D
OUT
Output Disable
3
V
IH
V
IL
V
IH
V
IH
X
High-Z
Any Valid SRAM Mode
High-Z
Standby
3
V
IH
V
IH
X
X
X
High-Z
High-Z
Reset
3
V
IL
X
X
X
X
High-Z
High-Z
Write
4, 5
V
IH
V
IL
V
IH
V
IL
V
IL
High-Z
SRAM must be in High Z
D
IN
SRAM
Read
5
Flash must be in High-Z
High-Z
V
IL
V
IH
V
IL
V
IH
V
IL
D
OUT
Output Disable
3
Any Valid FLASH Mode
V
IL
V
IH
V
IH
V
IH
X
High-Z
Standby and
Data Retention
3, 6
V
IH
X
X
X
X
High-Z
X
V
IL
X
X
X
High-Z
Write
5
Flash must be in High-Z
High-Z
V
IL
V
IH
V
IH
V
IL
V
IL
D
IN
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