參數(shù)資料
型號(hào)： 28F320B3
廠商： Intel Corp.
英文描述： SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY
中文描述： 智能高級(jí)啟動(dòng)3座4 - ，8 - ，16 - ，32 - Mbit閃存家庭
文件頁(yè)數(shù)： 61/82頁(yè)
文件大?。?/td> 749K
代理商： 28F320B3
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Preliminary
55
13.2
SRAM Write Operation
NOTES:
1. See
Figure 26,
“
AC Waveform: SRAM Write Operation
”
on page 56
.
2. A write occurs during the overlap (t
) of low S-CS
# and low S-WE#. A write begins when S-CS
# goes low
and S-WE# goes low with asserting S-UB# and S-LB# for x16 operation. S-UB# and S-LB# must be tied
together to restrict x16 mode. A write ends at the earliest transition when S-CS
1
# goes high and S-WE# goes
high. The t
is measured from the beginning of write to the end of write.
3. t
CW
is measured from S-CS
# going low to end of write.
4. t
AS
is measured from the address valid to the beginning of write.
5. t
is measured from the end of write to the address change; t
WR
applied in case a write ends as S-CS
1
# or
S-WE# going high.
#
Sym
Parameter
1
Density
4/8 Mbit
Unit
S-V
CC
2.2 V
–
3.3 V
Speed
-70
-85
Note
Min
Max
Min
Max
W1
t
WC
Write Cycle Time
2
70
–
85
–
ns
W2
t
AS
Address Setup to S-WE# (S-CS
1
#) and S-UB#, S-LB# Going Low
4
0
–
0
–
ns
W3
t
WP
S-WE# (S-CS
1
#) Pulse Width
3
55
–
60
–
ns
W4
t
DW
Data to Write Time Overlap
30
–
35
–
ns
W5
t
AW
Address Setup to S-WE# (S-CS
1
#) Going High
60
–
70
–
ns
W6
t
CW
S-SC
# (S-WE#) Setup to S-WE# (S-CS
1
#) Going High and S-SC
2
Going Low
60
–
70
–
ns
W7
t
DH
Data Hold Time from S-WE# (S-CS
1
#) High
0
–
0
–
ns
W8
t
WR
Write Recovery
5
0
–
0
–
ns
W9
t
BW
S-UB#, S-LB# Setup to S-WE# (S-CS
1
#) Going High
60
–
70
–
ns
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