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參數(shù)資料
| 型號： | 28F320J5 |
| 廠商： | Intel Corp. |
| 英文描述： | 5 Volt Intel StrataFlash Memory(5 V 32M位英特爾StrataFlash存儲器) |
| 中文描述： | 5伏英特爾StrataFlash存儲器（5伏32兆位英特爾的StrataFlash存儲器） |
| 文件頁數(shù)： | 28/53頁 |
| 文件大?。?/td> | 272K |
| 代理商： | 28F320J5 |
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28F320J5/28F640J5
E
28
PRELIMINARY
Confirm is written to the device, an
“Invalid
Command/Sequence” error will be generated and
status register bits SR.5 and SR.4 will be set to a
“1.” For additional buffer writes, issue another Write
to Buffer setup command and check XSR.7.
If an error occurs while writing, the device will stop
writing, and status register bit SR.4 will be set to a
“1” to indicate a program failure. The internal WSM
verify only detects errors for “1”s that do not
successfully program to “0”s. If a program error is
detected, the status register should be cleared. Any
time SR.4 and/or SR.5 is set (e.g., a media failure
occurs during a program or an erase), the device
will not accept any more Write to Buffer commands.
Additionally, if the user attempts to program past an
erase block boundary with a Write to Buffer
command, the device will abort the write to buffer
operation. This will generate an “Invalid Command/
Sequence” error and status register bits SR.5 and
SR.4 will be set to a “1.”
Reliable buffered writes can only occur when
V
PEN
= V
PENH
. If a buffered write is attempted while
V
PEN
≤
V
PENLK
, status register bits SR.4 and SR.3
will be set to “1.” Buffered write attempts with
invalid V
CC
and V
PEN
voltages produce spurious
results and should not be attempted. Finally,
successful
programming
corresponding Block Lock-Bit be reset or, if set, that
RP# = V
HH
. If a buffered write is attempted when
the corresponding Block Lock-Bit is set and RP# =
V
IH
, SR.1 and SR.4 will be set to “1.” Buffered write
operations with V
IH
< RP# < V
HH
produce spurious
results and should not be attempted.
requires
that
the
4.9
Byte/Word Program Commands
Byte/Word program is executed by a two-cycle
command sequence. Byte/Word program setup
(standard 40H or alternate 10H) is written followed
by a second write that specifies the address and
data (latched on the rising edge of WE#). The WSM
then takes over, controlling the program and
program verify algorithms internally. After the
program
sequence
is
automatically outputs status register data when
read (see Figure 8). The CPU can detect the
completion of the program event by analyzing the
STS pin or status register bit SR.7.
written,
the
device
When program is complete, status register bit SR.4
should be checked. If a program error is detected,
the status register should be cleared. The internal
WSM verify only detects errors for “1”s that do not
successfully program to “0”s. The CUI remains in
read status register mode until it receives another
command.
Reliable byte/word programs can only occur when
V
CC
and V
PEN
are valid. If a byte/word program is
attempted while V
PEN
≤
V
PENLK
, status register bits
SR.4 and SR.3 will be set to “1.” Successful
byte/word programs require that the corresponding
block lock-bit be cleared or, if set, that RP# = V
HH
.
If a byte/word program is attempted when the
corresponding block lock-bit is set and RP# = V
IH
,
SR.1 and SR.4 will be set to “1.” Byte/word program
operations with V
IH
< RP# < V
HH
produce spurious
results and should not be attempted.
4.10
Configuration Command
The Status (STS) pin can be configured to different
states using the Configuration command. Once the
STS pin has been configured, it remains in that
configuration until another configuration command
is issued or RP# is asserted low. Initially, the STS
pin defaults to RY/BY# operation where RY/BY#
low indicates that the state machine is busy.
RY/BY# high indicates that the state machine is
ready for a new operation or suspended. Table 15
displays the possible STS configurations.
To reconfigure the Status (STS) pin to other modes,
the Configuration command is given followed by the
desired configuration code. The three alternate
configurations are all pulse mode for use as a
system interrupt as described below. For these
configurations, bit 0 controls Erase Complete
interrupt pulse, and bit 1 controls Program
Complete interrupt pulse. Supplying the 00h
configuration code with the Configuration command
resets the STS pin to the default RY/BY# level
mode. The possible configurations and their usage
are described in Table 15. The Configuration
command may only be given when the device is not
busy or suspended. Check SR.7 for device status.
An invalid configuration code will result in both
status register bits SR.4 and SR.5 being set to “1.”
When configured in one of the pulse modes, the
STS pin pulses low with a typical pulse width of
250 ns.
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