參數(shù)資料
型號(hào)： 28F320J5
廠商： Intel Corp.
英文描述： 5 Volt Intel StrataFlash Memory(5 V 32M位英特爾StrataFlash存儲(chǔ)器)
中文描述： 5伏英特爾StrataFlash存儲(chǔ)器（5伏32兆位英特爾的StrataFlash存儲(chǔ)器）
文件頁(yè)數(shù)： 29/53頁(yè)
文件大小： 272K
代理商： 28F320J5
E
4.11
28F320J5/28F640J5
29
PRELIMINARY
Set Block and Master Lock-Bit
Commands
A flexible block locking and unlocking scheme is
enabled via a combination of block lock-bits and a
master lock-bit. The block lock-bits gate program
and erase operations while the master lock-bit
gates block-lock bit modification. With the master
lock-bit not set, individual block lock-bits can be set
using the Set Block Lock-Bit command. The Set
Master Lock-Bit command, in conjunction with
RP# = V
HH
, sets the master lock-bit. After the
master lock-bit is set, subsequent setting of block
lock-bits requires both the Set Block Lock-Bit
command and V
HH
on the RP# pin. These
commands are invalid while the WSM is running or
the device is suspended. See Table 14 for a
summary of hardware and software write protection
options.
Set block lock-bit and master lock-bit commands
are executed by a two-cycle sequence. The set
block or master lock-bit setup along with
appropriate block or device address is written
followed by either the set block lock-bit confirm (and
an address within the block to be locked) or the set
master lock-bit confirm (and any device address).
The WSM then controls the set lock-bit algorithm.
After the sequence is written, the device
automatically outputs status register data when
read (see Figure 11). The CPU can detect the
completion of the set lock-bit event by analyzing the
STS pin output or status register bit SR.7.
When the set lock-bit operation is complete, status
register bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The
CUI will remain in read status register mode until a
new command is issued.
This two-step sequence of set-up followed by
execution ensures that lock-bits are not accidentally
set. An invalid Set Block or Master Lock-Bit
command will result in status register bits SR.4 and
SR.5 being set to
“1.” Also, reliable operations
occur only when V
CC
and V
PEN
are valid. With V
PEN
≤
V
PENLK
, lock-bit contents are protected against
alteration.
A successful set block lock-bit operation requires
that the master lock-bit be zero or, if the master
lock-bit is set, that RP# = V
HH
. If it is attempted with
the master lock-bit set and RP# = V
IH
, SR.1 and
SR.4 will be set to “1” and the operation will fail. Set
block lock-bit operations while V
IH
< RP# < V
HH
produce spurious results and should not be
attempted. A successful set master lock-bit
operation requires that RP# = V
HH
. If it is attempted
with RP# = V
IH
, SR.1 and SR.4 will be set to “1”
and the operation will fail. Set master lock-bit
operations with V
IH
< RP# < V
HH
produce spurious
results and should not be attempted.
4.12
Clear Block Lock-Bits
Command
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With the master
lock-bit not set, block lock-bits can be cleared using
only the Clear Block Lock-Bits command. If the
master lock-bit is set, clearing block lock-bits
requires both the Clear Block Lock-Bits command
and V
HH
on the RP# pin. This command is invalid
while the WSM is running or the device is
suspended. See Table 14 for a summary of
hardware and software write protection options.
Clear block lock-bits command is executed by a
two-cycle sequence. A clear block lock-bits setup is
first written. The device automatically outputs status
register data when read (see Figure 12). The CPU
can detect completion of the clear block lock-bits
event by analyzing the STS pin output or status
register bit SR.7.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bit
error is detected, the status register should be
cleared. The CUI will remain in read status register
mode until another command is issued.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block
Lock-Bits command sequence will result in status
register bits SR.4 and SR.5 being set to “1.” Also, a
reliable clear block lock-bits operation can only
occur when V
CC
and V
PEN
are valid. If a clear block
lock-bits operation is attempted while V
PEN
≤
V
PENLK
, SR.3 and SR.5 will be set to “1.” A
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