參數資料
型號： 29F016-90
廠商： Macronix International Co., Ltd.
英文描述： 16M-BIT [2M X 8] CMOS EQUAL SECTOR FLASH MEMORY
中文描述： 1,600位[2米x 8]的CMOS平等部門閃存
文件頁數： 8/37頁
文件大?。?/td> 888K
代理商： 29F016-90
8
P/N:PM0590
REV. 1.4, NOV. 21, 2002
MX29F016
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command
register. Microprocessor read cycles retrieve array
data. The device remains enabled for reads until the
command register contents are altered.
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid command
must then be written to place the device in the desired
state.
SILICON-ID-READ COMMAND
Flash memories are intended for use in applications
where the local CPU alters memory contents. As such,
manufacturer and device codes must be accessible
while the device resides in the target system. PROM
programmers typically access signature codes by raising
A9 to a high voltage. However, multiplexing high voltage
onto address lines is not generally desired system
design practice.
The MX29F016 contains a Silicon-ID-Read operation to
supplement traditional PROM programming
methodology. The operation is initiated by writing the
read silicon ID command sequence into the command
register. Following the command write, a read cycle with
A1=VIL,A0=VIL retrieves the manufacturer code of C2H.
A read cycle with A1=VIL, A0=VIH returns the device
code of ADH for MX29F016.
SET-UP AUTOMATIC CHIP/SECTOR ERASE
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cycles
are then followed by the chip erase command 10H.
The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the
Automatic Chip Erase. Upon executing the Automatic
Chip Erase, the device will automatically program and
verify the entire memory for an all-zero data pattern.
When the device is automatically verified to contain an
all-zero pattern, a self-timed chip erase and verify begin.
The erase and verify operations are completed when the
data on Q7 is "1" at which time the device returns to the
Read mode. The system is not required to provide any
control or timing during these operations.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array(no
erase verification command is required).
If the Erase operation was unsuccessful, the data on Q5
is "1"(see Table 4), indicating the erase operation exceed
internal timing limit.
The automatic erase begins on the rising edge of the last
WE pulse in the command sequence and terminates
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode.
Pins
Manufacture code
Device code for MX29F016
A0
VIL
VIH
A1
VIL
VIL
Q7
1
1
Q6
1
0
Q5
0
1
Q4
0
0
Q3
0
1
Q2
0
1
Q1
1
0
Q0
0
1
Code(Hex)
C2H
ADH
TABLE 3. SILICON ID CODE
相關PDF資料
PDF描述
29F022B-12 2M-BIT[256K x 8]CMOS FLASH MEMORY
29F022B-120 2M-BIT[256K x 8]CMOS FLASH MEMORY
29F022B-55 2M-BIT[256K x 8]CMOS FLASH MEMORY
29F022B-70 2M-BIT[256K x 8]CMOS FLASH MEMORY
29F022B-90 2M-BIT[256K x 8]CMOS FLASH MEMORY
相關代理商/技術參數
參數描述
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29F020 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:2 Megabit (256 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory
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29F022B-120 制造商:MCNIX 制造商全稱:Macronix International 功能描述:2M-BIT[256K x 8]CMOS FLASH MEMORY
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