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16
Evaluating and Programming the 29K RISC Family
2–cycle minimum access times ensures that the address bus has more time to settle
before the data bus is driven. This reduces system noise compared with the data bus
changing state during the same cycle as the address bus.
At high processor clock rates, it is likely that an interleafed memory system will
be required to obtain bandwidths able to sustain 1–cycle burst mode access. Inter-
leafing requires the construction of two, four or more memory systems (known as
banks), which are used in sequence. When accessed in burst–mode, each bank is giv-
en more time to provide access to its next storage location. The processor provides an
input pin, EARLYA (early address), by which a memory system can request early ad-
dress generation by the processor. This can be used to simplify the implementation of
interleaved memory systems. When requested, the processor provides early the ad-
dress of even–addressed banks, allowing the memory system to begin early accesses
to both even– and odd–addressed banks.
The processor can operate with memory devices which are not the full 32–bit
width of the data bus. This is achieved using the Narrow Read capability. Memory
systems which are only 8–bit or 16–bit wide are connected to the upper bits of the
data/instruction bus. They assert the RDN (read narrow) input pin along with the
RDY (ready) pin when responding to access requests. When this occurs the processor
will automatically perform the necessary sequences of accesses to assemble instruc-
tions or data which are bigger than the memory system width.
The Narrow Read ability can not be used for data writing. However, it is very
useful for interfacing to ROM which contains system boot–up code. Only a single
8–bit ROM may be required to contain all the necessary system initialization code.
This can greatly simplify system design, board space, and cost. The ROM can be used
to initialize system RAM memory which, due to its 32–bit width, will permit faster
execution.
1.5.1 Am29030 Evaluation.
AMD provides a low cost evaluation board for the Am29030 at 16 MHz, known
as the EZ030 (pronounced easy–030). Like the microcontroller evaluation board, it is
a standalone, requiring an external 5v power supply and connection to a remote com-
puter via an RS–232 connection. The board is very small, measuring about 4 inches
by 4 inches (10x10 cm). The memory system is restricted to 16 MHz operation but
with scalable clocking the processor can run at 16 MHz or 33 MHz.
It contains 128k bytes of EPROM, which is accessed via 8–bit narrow bus proto-
col. There is also 1M byte of DRAM arranged as 256kx32 bits. The DRAM is ex-
pandable to 4M bytes. The EPROM is preprogrammed with the MiniMON29K de-
bug monitor and the OS–boot operating system described in Chapter 7.
1.5.2 The Am29035
The Am29035
processor is pin compatible with other 2–bus members of the
family (see Table 1-2). As would be expected, given the AMD product number, its