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Chapter 1 Architectural Overview
libraries. The TLB entries have a Global Page (GLB) bit; when set the mapped page
can be accessed by any processes regardless of its process identifier (PID). The TLB
also enables parity checking to be enabled on a per page basis; and pages can be allo-
cated from 16–bit or 32–bit wide memory regions.
On–chip debug support is extended with the inclusion of two Instruction Break-
point Controllers and one Data Breakpoint Controller. This enables inexpensive de-
bug monitors such as the DebugCore incorporated within MiniMON29K to be used
when developing software. Breakpoints are supported when physical or virtual ad-
dressing is in use. The JTAG test interface has also been extended over other 29K
family members to include several new JTAG–processed instructions. The effective-
ness of the JTAG interface for hardware and software debugging is improved.
The Am29040 family grouping is implemented with a silicon process which en-
ables processors to operate at 3.3–volts. However, the device is tolerant of 5–volt in-
put/output signal levels. The lower power consumption achievable at 3.3–volts
makes the Am29040 suitable for hand–held type applications. Note, the device oper-
ates at a maximum clock frequency of 50 MHz.
A 29K processor enters Wait Mode when the Wait Mode bit is set in the Current
Processor Status (CPS) register. Wait Mode is extended to include a Snooze Mode
which is entered from Wait Mode while the interrupt and trap input lines are held in-
active. An interrupt is normally used to depart Wait or Snooze Mode. While in
Snooze mode, Am29040 power consumption is reduced. Returning from Snooze
mode to an interrupt processing state requires approximately 256 cycles. The proces-
sor can be prevented from entering Snooze Mode while in Wait Mode by holding, for
example, the INTR3 input pin active and setting the interrupt mask such as to disable
the INTR3 interrupt.
If the input clock is held high or low while the processor is in Snooze mode,
Sleep Mode is entered. Minimum power consumption occurs in this mode. The pro-
cessor returns to Snooze Mode when the input clock is restarted. Using Snooze and
Sleep modes enables the Am29040 processor to be used in applications which are
very power sensitive.
1.6.1 Am29040 Evaluation.
Like any 29K processor, the Am29040 can be evaluated using the Architectural
Simulator. But for those who wish for real hardware, AMD manufactures a number
of evaluation boards. The most popular being the SE29040 evaluation board. The
board, originally constructed in rev–A form, supports 4M bytes of DRAM (expand-
able to 64M bytes); DRAM timing is 3/1, i.e. 3–cycle first access then 1–cycle burst.
There is also 1M byte of 32–bit wide ROM and space for 1M byte of 2/1 SRAM.
Boards are typically populated with only 128K of SRAM. The memory system clock
speed is 25 MHZ and the maximum processor speed of 50 MHz is supported.