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參數(shù)資料
| 型號(hào)： | 29LV800TE |
| 廠商： | Fujitsu Limited |
| 英文描述： | 8M (1M x 8/512 K x 16) BIT |
| 中文描述： | 8米（3米x五百一十二分之八畝× 16）位 |
| 文件頁數(shù)： | 24/58頁 |
| 文件大小： | 292K |
| 代理商： | 29LV800TE |
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MBM29LV800TE/BE
60/70/90
23
DQ
6
Toggle Bit I
The MBM29LV800TE/BE also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the
devices will result in DQ
6
toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle
is completed, DQ
6
will stop toggling and valid data will be read on the next successive attempts. During pro-
gramming, the Toggle Bit I is valid after the rising edge of the fourth WE pulses in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six
write pulses sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written is protected, the toggle bit will toggle for about 2
μ
s and then stop
toggling with data unchanged. In erase, devices will erase all selected sectors except for ones that are protected.
If all selected sectors are protected, the chip will toggle the toggle bit for about 200
μ
s and then drop back into
read mode, having data unchanged.
Either CE or OE toggling will cause DQ
6
to toggle. In addition, an Erase Suspend/Resume command will cause
DQ
6
to toggle.
See “Taggle Bit I during Embedded Algorithm Operation Timing Diagram” in “
I
TIMING DIAGRAM” for the
Toggle Bit I timing specifications and diagrams.
DQ
5
Exceeded Timing Limits
DQ
5
will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under
these conditions, DQ
5
will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of devices under this condition.
The CE circuit will partially power down device under these conditions (to approximately 2 mA) . The OE and
WE pins will control the output disable functions as described in “MBM29LV800TE/BE User Bus Operations
(BYTE = V
IH
)” and “MBM29LV800TE/BE User Bus Operations (BYTE = V
IL
)” in “
I
DEVICE BUS OPERATION”.
The DQ
5
failure condition may also appear if a user tries to program a non blank location without pre-erase. In
this case, the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
read valid data on DQ
7
bit and DQ
6
never stop toggling. Once devices have exceeded timing limits, the DQ
5
bit
will indicate a “1.” Please note that this is not a device failure condition since devices were incorrectly used. If
this occurs, reset device with command sequence.
DQ
3
Sector Erase Timer
After completion of the initial sector erase command sequence, sector erase time-out will begin. DQ
3
will remain
low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command
sequence.
If Data Polling or the Toggle Bit I indicates device has been written with a valid erase command, DQ
3
may be
used to determine if the sector erase timer window is still open. If DQ
3
is high (“1”) the internally controlled erase
cycle has begun : If DQ
3
is low (“0”) , the device will accept additional sector erase commands. To insure the
command has been accepted, the system software should check the status of DQ
3
prior to and following each
subsequent Sector Erase command. If DQ
3
were high on the second status check, the command may not have
been accepted.
See “Hardware Sequence Flags”.
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