參數(shù)資料
型號(hào)： 5962-0050401QXC
廠商： ATMEL CORP
元件分類： ADC
英文描述： 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
封裝： HEAT SPREADER, CERAMIC, QFP-68
文件頁數(shù)： 37/57頁
文件大?。?/td> 1276K
代理商： 5962-0050401QXC
Rev.2.10
Oct 25, 2006
Page 42 of 326
REJ03B0152-0210
M306H7MG-XXXFP/MC-XXXFP/FGFP
5.PROTECTION
5.
Protection
In the event that a program runs out of control, this function protects the important registers so that they will not be
rewritten easily. Figure 5.1 shows the PRCR register. The following lists the registers protected by the PRCR register.
Registers protected by PRC0 bit: CM0, CM1 and PCLKR registers
Registers protected by PRC1 bit: PM0, PM1 and PM2 registers
Registers protected by PRC2 bit: PD9, S3C and S4C registers
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0” (write
protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit
to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in which the PRC2 bit is set to “1”
and the next instruction. The PRC0 and PRC1 bits are not automatically cleared to “0” by writing to any address. They
can only be cleared in a program.
Figure 5.1
PRCR Register
Protect register
Symbol
Address
After reset
PRCR
000A16
XX0000002
Bit name
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
0 : Write protected
1 : Write enabled
PRC1
PRC0
PRC2
Function
RW
Note: The PRC2 bit is set to “0” by writing to any address after setting it to “1”. Other bits are not set to “0”
by writing to any address, and must therefore be set in a program.
00
RW
Nothing is assigned. When write, set to “0”. When read, its
content is interdeterminate.
Reserved bit
Must set to “0”
RW
Protect bit 0
Protect bit 1
Protect bit 2
Enable write to CM0, CM1 and
PCLKR registers
0 : Write protected
1 : Write enabled
Enable write to PM0, PM1 and
PM2 registers
0 : Write protected
1 : Write enabled
Enable write to PD9, S3C and
S4C registers
(b5-b3)
(b7-b6)
0
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