參數(shù)資料
型號(hào)： 5962-0050401QXC
廠商： ATMEL CORP
元件分類： ADC
英文描述： 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
封裝： HEAT SPREADER, CERAMIC, QFP-68
文件頁數(shù)： 50/57頁
文件大?。?/td> 1276K
代理商： 5962-0050401QXC
Rev.2.10
Oct 25, 2006
Page 54 of 326
REJ03B0152-0210
M306H7MG-XXXFP/MC-XXXFP/FGFP
6. INTERRUPTS
The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP(Note), at the
time of acceptance of an interrupt request, is even or odd. If the stack pointer (Note) is even, the FLG register and the
PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time. Figure 6.7 shows the operation
of the saving registers.
Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated by the U
flag. Otherwise, it is the ISP.
Figure 6.7
Operation of Saving Register
(2) SP contains odd number
[SP]
(Odd)
[SP] – 1 (Even)
[SP] – 2(Odd)
[SP] – 3 (Even)
[SP] – 4(Odd)
[SP] – 5 (Even)
Address
Sequence in which order
registers are saved
(2)
(1)
Finished saving registers
in four operations.
(3)
(4)
(1) SP contains even number
[SP]
(Even)
[SP] – 1(Odd)
[SP] – 2 (Even)
[SP] – 3(Odd)
[SP] – 4 (Even)
[SP] – 5 (Odd)
Note: [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Address
PCM
Stack
FLGL
PCL
Sequence in which order
registers are saved
(2)Saved simultaneously,
all 16 bits
(1)Saved simultaneously,
all 16 bits
Finished saving registers
in two operations.
PCM
Stack
FLGL
PCL
Saved, 8 bits at a time
FLGH
PCH
FLGH
PCH
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