參數(shù)資料
型號(hào)： 5962-0050401QXC
廠商： ATMEL CORP
元件分類： ADC
英文描述： 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
封裝： HEAT SPREADER, CERAMIC, QFP-68
文件頁(yè)數(shù)： 48/57頁(yè)
文件大?。?/td> 1276K
代理商： 5962-0050401QXC
Rev.2.10
Oct 25, 2006
Page 52 of 326
REJ03B0152-0210
M306H7MG-XXXFP/MC-XXXFP/FGFP
6. INTERRUPTS
6.10
Interrupt Response Time
Figure 6.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes a time
from when an interrupt request is generated till when the first instruction in the interrupt routine is executed.
Specifically, it consists of a time from when an interrupt request is generated till when the instruction then
executing is completed ((a) in Figure 6.5) and a time during which the interrupt sequence is executed ((b) in Figure
6.5).
Figure 6.5
Interrupt response time
6.11
Variation of IPL when Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed in Table
6.5 is set in the IPL. Shown in Table 6.5 are the IPL values of software and special interrupts when they are
accepted.
Table 6.5
IPL Level That is Set to IPL When A Software or Special Interrupt Is Accepted
Instruction
Interrupt sequence
Instruction in
interrupt routine
Time
Interrupt response time
(a)
(b)
Interrupt request acknowledged
Interrupt request generated
(a) A time from when an interrupt request is generated till when the instruction then
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
(b) A time during which the interrupt sequence is executed. For details, see the table
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.
Interrupt vector address
Even
Odd
SP value
Even
Odd
Even
Odd
16-Bit bus, without wait
18 cycles
19 cycles
20 cycles
8-Bit bus, without wait
20 cycles
Interrupt sources
7
Level that is set to IPL
Watchdog timer, NMI
Software, address match, DBC, single-step
Not changed
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