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參數(shù)資料
| 型號(hào)： | 5962-0050401QXC |
| 廠商： | ATMEL CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | HEAT SPREADER, CERAMIC, QFP-68 |
| 文件頁數(shù)： | 42/57頁 |
| 文件大?。?/td> | 1276K |
| 代理商： | 5962-0050401QXC |
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Rev.2.10
Oct 25, 2006
Page 47 of 326
REJ03B0152-0210
M306H7MG-XXXFP/MC-XXXFP/FGFP
6. INTERRUPTS
Relocatable Vector Tables
The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table
area. Table 6.2 lists the relocatable vector tables. Setting an even address in the INTB register results in the
interrupt sequence being executed faster than in the case of odd addresses.
Table 6.2
Relocatable Vector Tables
Software interrupt
number
Reference
Notes 1: Address relative to address in INTB
.
Notes 2: Use the IFSR register's IFSR6 and IFSR7 bits to select.
Notes 3: During I2C mode, NACK and ACK interrupts comprise the interrupt source.
Notes 4: Use the IFSR2A register’s IFSR26 and IFSR27 bits to select.
Notes 5: These interrupts cannot be disabled using the I flag.
Vector address (Note 1)
Address (L) to address (H)
0
11
12
14
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
63
to
10
15
16
5
6
7
8
4
9
1 to 3
Interrupt source
BRK instruction
INT3
SI/O3, INT4
SI/O4, INT5
Timer B4/Remote control, UART1 bus
collision detect
Timer B5/SLICE ON (Note 7)
(Note 2)
DMA0
DMA1
A/D
UART0 transmit, NACK0
UART0 receive, ACK0
UART1 transmit, NACK1
UART1 receive, ACK1
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4/Multi-master I C (Note 9)
Timer B0
Timer B1
Timer B2/Clock timer (Note 7)
INT0
INT1
INT2/Remote control transmission (Note 8)
Software interrupt
UART 2 bus collision detection
UART2 transmit, NACK2 (Note 3)
UART2 receive, ACK2 (Note 3)
(Note 4, Note 6, Note 7)
Timer B3/HINT, UART0 bus collision
detect
M16C/60, M16C/20
series software
manual
INT interrupt
Timer
Serial I/O
INT interrupt
Serial I/O
DMAC
A/D converter
Serial I/O
Timer
INT interrupt
M16C/60, M16C/20
series software
manual
(Note 5)
(Reserved)
+0 to +3 (000016 to 000316)
+44 to +47 (002C16 to 002F16)
+48 to +51 (003016 to 003316)
+56 to +59 (003816 to 003B16)
+68 to +71 (004416 to 004716)
+72 to +75 (004816 to 004B16)
+76 to +79 (004C16 to 004F16)
+80 to +83 (005016 to 005316)
+84 to +87 (005416 to 005716)
+88 to +91 (005816 to 005B16)
+92 to +95 (005C16 to 005F16)
+96 to +99 (006016 to 006316)
+100 to +103 (006416 to 006716)
+104 to +107 (006816 to 006B16)
+108 to +111 (006C16 to 006F16)
+112 to +115 (007016 to 007316)
+116 to +119 (007416 to 007716)
+120 to +123 (007816 to 007B16)
+124 to +127 (007C16 to 007F16)
+128 to +131 (008016 to 008316)
+252 to +255 (00FC16 to 00FF16)
+40 to +43 (002816 to 002B16)
+60 to +63 (003C16 to 003F16)
+64 to +67 (004016 to 004316)
+20 to +23 (001416 to 001716)
+24 to +27 (001816 to 001B16)
+28 to +31 (001C16 to 001F16)
+32 to +35 (002016 to 002316)
+16 to +19 (001016 to 001316)
+36 to +39 (002416 to 002716)
to
(Note 3)
(Note 5)
Notes 6: Bus collision detection : During IE mode, this bus collision detection constitutes the cause of an interrupt.
Notes 7: When you use SLICEON, remote control, HINT and clock timer interruption, refer to address 3616 expansion
register of “14. Expansion Function”
Notes 8: Please refer to address 3E16 of the expansion register of “14. Expansion Function” when you use the remote
control transmission interrupt.
Notes 9: Please refer to the I2C0 interrupt control register of “11 multi-master I2C-BUS interface” (address 02D616) when
you use multi master I2C interrupt.
During I2C mode, however, a start condition or a stop condition detection
constitutes the cause of an interrupt.
2
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