參數(shù)資料
型號(hào): 5962-0050401QYC
廠商: E2V TECHNOLOGIES PLC
元件分類: ADC
英文描述: 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QFP68
封裝: QFP-68
文件頁數(shù): 45/57頁
文件大?。?/td> 1276K
代理商: 5962-0050401QYC
5
TS8388B
2144C–BDC–04/03
Positive supply current
Analog
Digital
I
CC
IPLUSD
1, 2
6
1, 2
6
385
395
115
120
445
145
mA
Negative supply voltage
VEE
1, 2, 6
-5.3
-5
-4.7
V
Negative supply current
Analog
Digital
AIEE
DIEE
1, 2
6
1, 2
6
165
170
135
145
200
180
mA
Nominal power dissipation
PD
1, 2
6
3.4
3.6
4.1
4.3
W
Power supply rejection ratio
PSRR
4
0.5
2
mW
Resolution
8
bits
Analog Inputs
Full Scale Input Voltage range (differential mode)
(0V common mode voltage)
VIN
VINB
4
-125
125
mV
Full Scale Input Voltage range (single-ended input
option) (See Application Notes)
V
IN
VINB
4
-250
0
250
mV
Analog input capacitance
C
IN
4–
3
3.5
pF
Input bias current
I
IN
4
10
20
A
Input Resistance
RIN
40.5
1
M
Full Power input Bandwidth (-3dB)
CBGA68 package
CQFP68 package
FPBW
4
1.8
1.5
GHz
Small signal input Bandwidth (10% full scale)
SSBW
4
1.5
1.7
GHz
Clock Inputs
Logic compatibility for clock inputs
(See Application Notes)
––
ECL or specified clock input
power level in dBm
ECL Clock inputs voltages (V
CLK or VCLKB):
4
–––
Logic “0” voltage
VIL
––
-1.5
V
Logic “1” voltage
V
IH
–-1.1
V
Logic “0” current
I
IL
––
5
50
A
Logic “1” current
IIH
––
5
50
A
Clock input power level into 50
termination
dBm into 50
Clock input power level
4
-2
4
10
dBm
Clock input capacitance
CCLK
4–
3
3.5
pF
Table 3. Electrical Specifications (Continued)
Parameter
Symbol
Test
Level
Value
Unit
Note
Min
Typ
Max
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