參數(shù)資料
型號(hào)： 5962-0050401QYC
廠商： E2V TECHNOLOGIES PLC
元件分類(lèi)： ADC
英文描述： 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QFP68
封裝： QFP-68
文件頁(yè)數(shù)： 53/57頁(yè)
文件大小： 1276K
代理商： 5962-0050401QYC
Rev.2.10
Oct 25, 2006
Page 57 of 326
REJ03B0152-0210
M306H7MG-XXXFP/MC-XXXFP/FGFP
6. INTERRUPTS
6.16
INT Interrupt
INTi interrupt (i = 0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the IFSR
register's IFSRi bit.
INT4 and INT5 share the interrupt vector and interrupt control register with SI/O3 and SI/O4, respectively.
To use the INT4 interrupt, set the IFSR register’s IFSR6 bit to “1” (= INT4). To use the INT5 interrupt, set the IFSR
register’s IFSR7 bit to “1” (= INT5).
After modifying the IFSR6 or IFSR7 bit, clear the corresponding IR bit to “0” (= interrupt not requested) before
enabling the interrupt.
INT2 and the remote control transmission, the vector and the interrupt control register are shared. (Please refer to
“14. Expansion Function” for details. )
Figure 6.10 shows the IFSR and IFSR2A registers.
Figure 6.10
IFSR Register and IFSR2A Register
Interrupt request cause select register
Bit name
Function
Bit symbol
RW
Symbol
Address
After reset
Symbol
Address
After reset
IFSR
035F16
0016
IFSR0
b7
b6
b5
b4
b3
b2
b1
b0
INT0 interrupt polarity
switching bit
0 : SI/O3
1 : INT4
0 : SI/O4
1 : INT5
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
INT1 interrupt polarity
switching bit
INT2 interrupt polarity
switching bit
INT3 interrupt polarity
switching bit
INT4 interrupt polarity
switching bit
INT5 interrupt polarity
switching bit
0 : One edge
1 : Both edges
Interrupt request cause
select bit
Interrupt request cause
select bit
IFSR1
IFSR2
IFSR3
IFSR4
IFSR5
IFSR6
IFSR7
RW
(Note 1)
(Note 2)
Note 1: When setting this bit to “1” (= both edges), make sure the INT0IC to INT5IC register’s POL bit
is set to “0” (= falling edge).
Note 2: When setting this bit to “0” (= SI/O3, SI/O4), make sure the S3IC and S4IC registers’ POL bit is
set to “0” (= falling edge).
(Note 2)
Interrupt request cause select register 2
Bit name
Function
Bit symbol
RW
IFSR2A
035E16
00XXXXXX2
b7
b6
b5
b4
b3
b2
b1
b0
0 : Timer B3/HINT
1 : UART0 bus collision
detection
0 : Timer B4/Remote control
1 : UART1 bus collision
detection
IFSR26
IFSR27
Interrupt request cause
select bit (Note 1)
Interrupt request cause
select bit (Note 2)
RW
(b5-b0)
Nothing is assigned. When write, set to “0”.
When read, their contents are indeterminate.
Note 1: Timer B3/HINT and UART0 bus collision detection share the vector and interrupt control register. When using
the timer B3/HINT interrupt, clear the IFSR26 bit to “0” (timer B3/HINT). When using UART0 bus collision
detection, set the IFSR26 bit to “1”.
Note 2: Timer B4/Remote control and UART1 bus collision detection share the vector and interrupt control register.
When using the timer B4/Remote control interrupt, clear the IFSR27 bit to “0” (timer B4/Remote control).
When using UART1 bus collision detection, set the IFSR27 bit to “1”.
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