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| 型號： | 5962-0050401QYC |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QFP68 |
| 封裝： | QFP-68 |
| 文件頁數(shù)： | 49/57頁 |
| 文件大?。?/td> | 1276K |
| 代理商： | 5962-0050401QYC |
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Rev.2.10
Oct 25, 2006
Page 53 of 326
REJ03B0152-0210
M306H7MG-XXXFP/MC-XXXFP/FGFP
6. INTERRUPTS
6.12
Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG register, 16
bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure 6.6 shows the stack
status before and after an interrupt request is accepted.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use the PUSHM
instruction, and all registers except SP can be saved with a single instruction.
Figure 6.6
Stack Status Before and After Acceptance of Interrupt Request
Address
Content of previous stack
Stack
[SP]
SP value before
interrupt occurs
m
m – 1
m – 2
m – 3
m – 4
Stack status before interrupt request
is acknowledged
Stack status after interrupt request
is acknowledged
Content of previous stack
m + 1
MSB
LSB
m
m – 1
m – 2
m – 3
m – 4
Address
FLGL
Content of previous stack
Stack
FLGH
PCH
[SP]
New SP value
Content of previous stack
m + 1
MSB
LSB
PC L
PCM
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| 5962-0050601Q2A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS |
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