參數(shù)資料
型號： 5962-0050401QYC
廠商： ATMEL CORP
元件分類： ADC
英文描述： 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
封裝： CERAMIC, QFP-68
文件頁數(shù)： 46/57頁
文件大?。?/td> 1276K
代理商： 5962-0050401QYC
Rev.2.10
Oct 25, 2006
Page 50 of 326
REJ03B0152-0210
M306H7MG-XXXFP/MC-XXXFP/FGFP
6. INTERRUPTS
6.6
I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the maskable
interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts.
6.7
IR Bit
The IR bit is set to “1” (= interrupt requested) when an interrupt request is generated. Then, when the interrupt
request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is cleared to “0” (=
interrupt not requested).
The IR bit can be cleared to “0” in a program. Note that do not write “1” to this bit.
6.8
ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 6.3 shows the settings of interrupt priority levels and Table 6.4 shows the interrupt priority levels
enabled by the IPL.
The following are conditions under which an interrupt is accepted:
I flag = “1”
IR bit = “1”
interrupt priority level > IPL
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one another.
ILVL2 to ILVL0 bits
Interrupt priority
level
Priority
order
0002
0012
0102
0112
1002
1012
1102
1112
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Low
High
Enabled interrupt priority levels
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
IPL
0002
0012
0102
0112
1002
1012
1102
1112
Table 6.3
Settings of Interrupt Priority
Levels
Table 6.4
Interrupt Priority Levels Enabled
by IPL
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