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參數(shù)資料
| 型號： | 5962-0051901NXD |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| 封裝： | PLASTIC, TSSOP-32 |
| 文件頁數(shù)： | 13/42頁 |
| 文件大?。?/td> | 840K |
| 代理商： | 5962-0051901NXD |
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THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
20
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DATA_AV type
Bit 4 and bit 5 (DATA_T, DATA_P) of control register 1 are used to program the signal DATA_AV. Bit 4 of
control register 1 determines whether the DATA_AV signal is static or a pulse. Bit 5 of the control register
determines the polarity of DATA_AV. This is shown in Table 14.
Table 14. DATA_AV Type
BIT 5
DATA_P
BIT 4
DATA_T
DATA_AV TYPE
0
Active low level
0
1
Active low pulse
1
0
Active high level
1
Active high pulse
The signal DATA_AV is set to active when the trigger condition is satisfied. It is set back inactive dependent of
the DATA_T selection (pulse or level).
If level mode is chosen, DATA_AV is set inactive after the first of the TL (TL = trigger level) reads (with the falling
edge of READ). The trigger condition is checked again after TL reads. For single conversion mode, DATA_AV
type should be programmed to active level mode (set bit 4 of CR1 to zero).
If pulse mode is chosen, the signal DATA_AV is a pulse with a width of one half of a CONV_CLK cycle in
continuous conversion mode. When the TL values previously written into the FIFO were read out by the
processor, the next DATA_AV pulse (when the trigger condition is satisfied) is sent out first.
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| 5962-0052201HXA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DC to DC Converter |
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