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參數(shù)資料
| 型號： | 5962-0051901NXD |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| 封裝： | PLASTIC, TSSOP-32 |
| 文件頁數(shù)： | 9/42頁 |
| 文件大小： | 840K |
| 代理商： | 5962-0051901NXD |
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THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
analog input channel selection
The analog input channels of the THS12082 can be selected via bits 3 to 7 of control register 0. One single
channel (single-ended or differential) is selected via bit 3 and bit 4 of control register 0. Bit 5 controls the
selection between single-ended and differential configuration. Bit 6 and bit 7 select the autoscan mode, if more
than one input channel is selected. Table 10 shows the possible selections.
Table 10. Analog Input Channel Configurations
BIT 7
AS
BIT 6
DF1
BIT 5
DF0
BIT 4
CHS1
BIT 3
CHS0
DESCRIPTION OF THE SELECTED INPUTS
0
Analog input AINP (single ended)
0
1
Analog input AINM (single ended)
0
1
0
Reserved
0
1
Reserved
0
1
0
Differential channel (AINP–AINM)
0
1
0
1
Reserved
1
0
1
Autoscan two single ended channels: AINP, AINM, AINP,
…
1
0
1
0
Reserved
1
0
1
Reserved
1
0
1
Reserved
1
0
1
0
1
Reserved
1
0
1
0
Reserved
0
1
0
Reserved
0
1
Reserved
1
0
Reserved
1
0
1
0
Reserved
1
0
1
Reserved
1
0
Reserved
1
0
1
0
Reserved
1
0
1
Reserved
1
0
Reserved
1
0
1
Reserved
1
0
Reserved
1
Reserved
test mode
The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The different selections are shown
in Table 11.
Table 11. Test Mode
BIT 9
TEST1
BIT 8
TEST0
OUTPUT RESULT
0
Normal mode
0
1
VREFP
1
0
((VREFM)+(VREFP))/2
1
VREFM
Three different options can be selected. This feature allows support testing of hardware connections between
the ADC and the processor.
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