參數(shù)資料
型號(hào)： 5962-0051901NXD
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
封裝： PLASTIC, TSSOP-32
文件頁(yè)數(shù)： 14/42頁(yè)
文件大?。?/td> 840K
代理商： 5962-0051901NXD
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing and signal description of the THS12082
read timing (using R/W, CS0-controlled)
Figure 11 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write
input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled
because CS0 is the last external signal of CS0, CS1, and R/W that becomes valid.
90%
10%
tw(CS)
tsu(R/W)
th(R/W)
ta
th
td(CSDAV)
CS0
CS1
R/W
RD
D(0–11)
DATA_AV
Figure 11. Read Timing Diagram Using R/W (CS0-controlled)
read timing parameter (CS0-controlled)
PARAMETER
MIN
TYP
MAX
UNIT
tsu(R/W)
Setup time, R/W high to last CS valid
0
ns
ta
Access time, last CS valid to data valid
0
10
ns
td(CSDAV) Delay time, last CS valid to DATA_AV inactive
12
ns
th
Hold time, first CS invalid to data invalid
0
5
ns
th(R/W)
Hold time, first external CS invalid to R/W change
5
ns
tw(CS)
Pulse duration, CS active
10
ns
CS = CSO
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