參數(shù)資料
型號: 73M1822-KEYCHN
廠商: Maxim Integrated Products
文件頁數(shù): 27/82頁
文件大?。?/td> 0K
描述: BOARD KEYCHAIN 73M1822 42-QFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
主要目的: *
嵌入式: *
已用 IC / 零件: *
主要屬性: *
次要屬性: *
已供物品: 板,CD
DS_1x22_017
73M1822/73M1922 Data Sheet
Rev. 1.6
33
5
Control and Status Registers
Table 30 shows the register map of addressable registers for the 73M1822 and 73M1922. The shaded
cells in the register map indicate read only and cannot be modified. Reserved bits should be left in their
default state. Accessing unspecified registers should be avoided. Each register and bit is described in
detail in the following sections.
For registers 0x12 through 0x1F, which are located in the Line-Side Device, there is a minimum time
between consecutive write transactions of 300
s.
Table 30: Control and Status Register Map
Address
(hex)
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01
00h/9Ch
Reserved
02
00h
Reserved
03
F0h
04
F7h
05
0Bh
06
00h
Reserved
07
00h
Reserved
08
DAh
09
EFh
0A
31h
Reserved
0B
2Ah
Reserved
0C
06h
0D
42h
Reserved
0E
00h
Reserved
0F
2Ch
Reserved
Reserved
10
00h
Reserved
12
00h
13
00h
14
00h
Reserved
15
00h
Reserved
Reserved
16
01h
17
00h
Reserved
Reserved
18
01h
Reserved
19
00h
Reserved
1A
00h
1B
00h
Reserved
1C
00h
Reserved
1D
90h
Reserved
1E
00h
Reserved
1F
00h
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