參數(shù)資料
型號: 73M1822-KEYCHN
廠商: Maxim Integrated Products
文件頁數(shù): 7/82頁
文件大?。?/td> 0K
描述: BOARD KEYCHAIN 73M1822 42-QFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
主要目的: *
嵌入式: *
已用 IC / 零件: *
主要屬性: *
次要屬性: *
已供物品: 板,CD
DS_1x22_001
73M1822/73M1922 Data Sheet
Rev. 1.6
15
2.5
73M1822 Pinout
Figure 6 shows the 73M1822 42-pin pinout.
73M1822
PRM
PRP
VPD/VPT
INT/RGDT
SCLK
SDIN
SDOUT
FSD
FS
VND
GP
IO
VND
VPD/
VPPL
L
O
SCI
N/
M
CL
K
O
SCO
UT
VNA
VNA/
VNPL
L
AO
UT
VPA/
VPM
VNA
M/
S
SRE
SRB
VBG
ACS
VNS
VPS
RXP
RXM
TXM
DCD
DCS
DCG
DCI
RG
N
RG
P
O
FH
M
20B
P
SCP
MID
VPX
VND/
VNX
1
2
3
4
5
6
7
8
9
10
20
11
12
13
14
15
16
17
18
19
21
22
23
24
25
26
27
28
29
30
31
32
33
35
34
36
37
38
39
40
41
42
Figure 6: 73M1822 42-Pin Pinout
Table 5 describes the pin functions for the device. Decoupling capacitors on the power supplies should be
included for each pair of supply pins.
Table 5: 73M1822 Pin Definitions
Pin
Number
Pin Name
Type
Description
1
PRP
I/O
Pulse transformer primary plus
2
PRM
I/O
Pulse transformer primary minus
3
VPD/VPT
PWR
Positive digital/transformer supply
4
INT/RGDT
O
Ring detection indicator or other Interrupts
Open drain
5
SCLK
O
Serial interface clock. With continuous SCLK selected,
Frequency = 256
Fs (=1.8432 MHz for Fs=7.2 kHz, 2.048 MHz
for Fs=8 kHz)
6
SDIN
I
Serial data input (or output from the controller to the 73M1822)
7
SDOUT
O
Serial data output (or input to the controller from the 73M1822)
8
FSD
O
FS delayed
9
FS
O
Frame synchronization
10
VND
GND
Negative digital ground
11
GPIO
I/O
Configurable digital input/output pins
12
VND
GND
Negative digital ground
13
VPD/VPPLL
PWR
Positive digital supply
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