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參數(shù)資料
| 型號(hào)： | 73M1822-KEYCHN |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 33/82頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD KEYCHAIN 73M1822 42-QFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | * |
| 嵌入式： | * |
| 已用 IC / 零件： | * |
| 主要屬性： | * |
| 次要屬性： | * |
| 已供物品： | 板，CD |
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DS_1x22_017
73M1822/73M1922 Data Sheet
Rev. 1.6
39
6.5
GPIO Registers
The 73M1922 32-pin QFN package provides four I/O pins (GPIO7, GPIO6, GPIO5 and GPIO4). The
73M1822 (42-pin QFN package) provides one user GPIO pin (GPIO6).
GPIO pins are not available on the 20-pin package version of the 73M1922.
Each pin can be configured independently as either an input or an output.
At power on and after a reset, the GPIO pins are initialized to a high impedance state to avoid unwanted
current contention and consumption. The input structures are protected from floating inputs, and no output
levels are driven by any of the GPIO pins.
The GPIO pins are configured as inputs or outputs by writing to the I/O Direction register (DIR).
The mapping of GPIO pins is designed to correspond to the bit location in their control and status registers.
The 73M1922 supports the ability to generate an interrupt on the INT pin. The source can be configured to
generate on a rising or a trailing edge. Only GPIO ports that are configured as inputs can be used to
generate interrupts.
Function
Mnemonic
Register
Location
Type
Description
DIR
0x04[7:4]
W
I/O Direction
These control bits are used to designate the GPIO[7:4] pins as either
inputs or outputs.
0 = GPIO pin is programmed to be an output.
1 = GPIO pin is programmed to be an input. (Default)
GPIOn
0x03[7:4]
W
GPIO Status
These bits reflect the status of the GPIO7, GPIO6, GPIO5 and GPIO4
pins.
If DIR bit is reset, reading this field will return the logical value of the
appropriate GPIOn pin as an input.
If DIR bit is set the pins will output the logical value as written.
ENGPIOn
0x05[7:4]
W
GPIO Interrupt Enable
Each of the GPIO enable bits in this register enables the
corresponding GPIO bit as an edge-triggered interrupt source. If a
GPIO bit is set to one, an edge (which edge depends on the value in
the GIP register) of the corresponding GPIO pin will cause the INT pin
to go active low, and the edge detectors will be rearmed when the
GPIO data register is read.
POLn
0x06[7:4]
W
GPIO Interrupt Edge Selection
Define the interrupt source as being either on a rising or a falling edge
of the corresponding GPIO pin.
0 = A rising edge will trigger an interrupt from the corresponding pin.
(Default)
1 = A falling edge will trigger an interrupt from the corresponding pin.
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