參數(shù)資料
型號(hào)： 73S1215F-68IM/F/P
廠商： Maxim Integrated Products
文件頁數(shù)： 124/136頁
文件大?。?/td> 0K
描述： IC SMART CARD READER PROG 68-QFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 260
系列： 73S12xx
核心處理器： 80515
芯體尺寸： 8-位
速度： 24MHz
連通性： I²C，智能卡，UART/USART，USB
外圍設(shè)備： LED，POR，WDT
輸入/輸出數(shù)： 9
程序存儲(chǔ)器容量： 64KB（64K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 68-VFQFN 裸露焊盤
包裝： 管件
73S1215F Data Sheet
DS_1215F_003
88
Rev. 1.4
Smart Card Interrupt Register (SCInt): 0xFE01
0x00
When the smart card interrupt is asserted, the firmware can read this register to determine the actual
cause of the interrupt. The bits are cleared when this register is read. Each interrupt can be disabled by
the Smart Card Interrupt Enable register. Error processing must be handled by the firmware. This
register relates to the interface that is active – see the SCSel register.
Table 82: The SCInt Register
MSB
LSB
WAITTO CRDEVT VCCTMRI
RXDAV
TXEVT
TXSENT
TXERR
RXERR
Bit
Symbol
Function
SCInt.7
WAITTO
Wait Timeout – An ATR or card wait timeout has occurred. In sync
mode, this interrupt is asserted when the RLen counter (it advances on
falling edges of CLK/ETU) reaches the loaded (max) value. This bit is
cleared when the SCInt register is read. When running in Synchronous
Clock Stop Mode, this bit becomes RLenINT interrupt (set when the Rlen
counter reaches the terminal count).
SCInt.6
CRDEVT
Card Event – A card event is signaled via pin DETCARD either when the
Card was inserted or removed (read the CRDCtl register to determine
card presence) or there was a fault condition in the interface circuitry.
This bit is functional even if the smart card logic clock is disabled and
when the PWRDN bit is set. This bit is cleared when the SCInt register is
read.
SCInt.5
VCCTMRI
VCC Timer – This bit is set when the VCCTMR times out. This bit is
cleared when the SCInt register is read.
SCInt.4
RXDAV
Rx Data Available – Data was received from the smart card because the
Rx FIFO is not empty. In bypass mode, this interrupt is generated on a
falling edge of the smart card I/O line. After receiving this interrupt in
bypass mode, firmware should disable it until the firmware has received
the entire byte and is waiting for the next start delimiter. This bit is
cleared when there is no RX data available in the RX FIFO.
SCInt.3
TXEVNT
TX Event – Set whenever the TXEMTY or TXFULL bits are set in the
SRXCtl SFR. This bit is cleared when the STXCtl register is read.
SCInt.2
TXSENT
TX Sent – Set whenever the ISO UART has successfully transmitted a
byte to the smart card. Also set when a CRC/LRC byte is sent in T=1
mode. Will not be set in T=0 when a break is detected at the end of a
byte (when break detection is enabled). This bit is cleared when the
SCInt register is read.
SCInt.1
TXERR
TX Error – An error was detected during the transmission of data to the
smart card as indicated by either BREAKD or TXUNDR bit being set in
the STXCtl SFR. Additional information can be found in that register
description. This bit is cleared when the STXCtl register is read.
SCInt.0
RXERR
RX Error – An error was detected during the reception of data from the
smart card. Additional information can be found in the SRXCtl register.
This interrupt will be asserted for RXOVRR, or RX Parity error events.
This bit is cleared when the SRXCtl register is read.
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