參數(shù)資料
型號： 73S1215F-68IM/F/P
廠商： Maxim Integrated Products
文件頁數(shù)： 133/136頁
文件大?。?/td> 0K
描述： IC SMART CARD READER PROG 68-QFN
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 260
系列： 73S12xx
核心處理器： 80515
芯體尺寸： 8-位
速度： 24MHz
連通性： I²C，智能卡，UART/USART，USB
外圍設(shè)備： LED，POR，WDT
輸入/輸出數(shù)： 9
程序存儲器容量： 64KB（64K x 8）
程序存儲器類型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 68-VFQFN 裸露焊盤
包裝： 管件
73S1215F Data Sheet
DS_1215F_003
96
Rev. 1.4
Smart Card Control Register (SCCtl): 0xFE0A
0x21
This register is used to monitor reception of data from the smart card.
Table 90: The SCCtl Register
MSB
LSB
RSTCRD
–
IO
IOD
C8
C4
CLKLVL
CLKOFF
Bit
Symbol
Function
SCCtl.7
RSTCRD
1 = Asserts the RST (set RST = 0) to the smart card interface, 0 = De-
assert the RST (set RST = 1) to the smart card interface. Can be used to
extend RST to the smart card. Refer to the RLength register description.
This bit is operational in all modes and can be used to extend RST during
activation or perform a “Warm Reset” as required. In auto-sequence
mode, this bit should be set = 0 to allow the sequencer to de-assert RST
per the RLength parameters.
In sync mode (see the SPrtcol register) the sense of this bit is non-
inverted, if set =1 , RST = 1, if set = 0, RST = 0. Rlen has no effect on
Reset in sync mode.
SCCtl.6
–
SCCtl.5
IO
Smart Card I/O. Read is state of I/O signal (Caution, this signal is not
synchronized to the MPU clock). In Bypass mode, write value is state of
signal on I/O. In sync mode, this bit will contain the value of I/O pin on
the latest rising edge of CLK.
SCCtl.4
IOD
Smart Card I/O Direction control Bypass mode or sync mode. 1 = input
(default), 0 = output.
SCCtl.3
C8
Smart Card C8. When C8 is an output, the value written to this bit will
appear on the C8 line. The value read when C8 is an output is the value
stored in the register. When C8 is an input, the value read is the value
on the C8 pin (Caution, this signal is not synchronized to the MPU clock).
When C8 is an input, the value written will be stored in the register but
not presented to the C8 pin.
SCCtl.2
C4
Smart Card C4. When C4 is an output, the value written to this bit will
appear on the C4 line. The value read when C4 is an output is the value
stored in the register. When C4 is an input, the value read is the value
on the C4 pin (Caution, this signal is not synchronized to the MPU clock).
When C4 is an input, the value written will be stored in the register but
not presented to the C4 pin.
SCCtl.1
CLKLVL
1 = High, 0 = Low. If CLKOFF is set = 1, the CLK to smart card will be at
the logic level indicated by this bit. If in bypass mode, this bit directly
controls the state of CLK.
SCCtl.0
CLKOFF
0 = CLK is enabled. 1 = CLK is not enabled. When asserted, the CLK
will stop at the level selected by CLKLVL. This bit has no effect if in
bypass mode.
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