參數(shù)資料
型號(hào)： 73S1215F-68IM/F/P
廠商： Maxim Integrated Products
文件頁數(shù)： 99/136頁
文件大?。?/td> 0K
描述： IC SMART CARD READER PROG 68-QFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 260
系列： 73S12xx
核心處理器： 80515
芯體尺寸： 8-位
速度： 24MHz
連通性： I²C，智能卡，UART/USART，USB
外圍設(shè)備： LED，POR，WDT
輸入/輸出數(shù)： 9
程序存儲(chǔ)器容量： 64KB（64K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 68-VFQFN 裸露焊盤
包裝： 管件
DS_1215F_003
73S1215F Data Sheet
Rev. 1.4
65
1.7.12 Keypad Interface
Keypad Interface
The 73S1215F supports a 30-button (6 row x 5 column) keypad (SPST Mechanical Contact Switches)
interface using 11 dedicated I/O pins.
The 73S1215F supports a 30-button (6 row x 5 column) keypad (SPST Mechanical Contact Switches)
interface using 11 dedicated I/O pins.
Figure 12 shows a simplified block diagram of the keypad interface.
Scan
pu
ll-
up
Debouncing
De
bo
unc
e
Tim
e
7
6
5
4
3
2 1
0
KSIZE Register
6
(1) KCOL is normally used as Read only
register. When hardware keyscan mode
is disabled, this register is to be used by
firmware to write the column data to
handle firmware scanning.
(2) 1kHz internal clock signal can be
selected either from the PLL (= from the
12MHz main clock), or from the 32kHz
system clock.
Ke
y_
De
te
ct
Hardware Scan Enable
6
Co
lu
mn
S
can
O
rd
er
5
Column Value
Row Value
Ke
y_
De
te
ct
_
E
n
a
b
le
KORDERL / H Registers
7
6 5
4
3
2 1
0
7
6 5
4
3
2
1
0
7
6
5
4 3
2
1
0
KCOL Register(1)
7
6
5
4 3
2
1
0
KROW Register
Dividers
1kHz (2)
Sca
n
Tim
e
KSCAN Register
7
6
5
4
3
2
1
0
7
6
5
4 3
2
1
0
KSTAT Register
Keypad Clock
VDD
pu
ll-
up
COL4:0
ROW
5:
0
73S1215F
If smaller keypad than 6 x 5 is to be
implemented, unused row inputs
should be connected to VDD. Unused
column outputs should be left
unconnected.
VDD
Figure 12: Simplified Keypad Block Diagram
There are 5 drive lines (outputs) corresponding to columns and 6 sense lines (inputs) corresponding to
rows. Hysteresis and pull-ups are provided on all inputs (rows), which eliminate the need for external
resistors in the keypad. Key scanning happens by asserting one of the 5 column lines low and looking for
a low on a sense line indicating that a key is pressed (switch closed) at the intersection of the drive/sense
(col/row) line in the keypad. Key detection is performed by hardware with an incorporated debounce
timer. Debouncing time is adjustable through the KSCAN register. Internal hardware circuitry performs
column scanning at an adjustable scanning rate and column scanning order through registers KSCAN
and KORDERL / KORDERH. Key scanning is disabled at reset and must be enabled by firmware. When
a valid key is detected, an interrupt is generated and the valid value of the pressed key is automatically
written into KCOL and KROW registers. The keypad interface uses a 1kHz clock derived from either the
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