參數(shù)資料
型號: 73S1215F-68IM/F/P
廠商: Maxim Integrated Products
文件頁數(shù): 62/136頁
文件大小: 0K
描述: IC SMART CARD READER PROG 68-QFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 260
系列: 73S12xx
核心處理器: 80515
芯體尺寸: 8-位
速度: 24MHz
連通性: I²C,智能卡,UART/USART,USB
外圍設備: LED,POR,WDT
輸入/輸出數(shù): 9
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 68-VFQFN 裸露焊盤
包裝: 管件
DS_1215F_003
73S1215F Data Sheet
Rev. 1.4
31
Master Clock Control Register (MCLKCtl): 0x8F
0x0A
Table 18: The MCLKCtl Register
MSB
LSB
HSOEN
KBEN
SCEN
USBEN 32KEN
MCT.2
MCT.1
MCT.0
Bit
Symbol
Function
MCLKCtl.7
HSOEN*
High-speed oscillator enable. When set = 1, disables the high-speed
crystal oscillator and VCO/PLL system. This bit is not changed when the
PWRDN bit is set but the oscillator/VCO/PLL is disabled.
MCLKCtl.6
KBEN
1 = Disable the keypad logic clock. This bit is not changed in PWRDN
mode but the function is disabled.
MCLKCtl.5
SCEN
1 = Disable the smart card logic clock. This bit is not changed in PWRDN
mode but the function is disabled. Interrupt logic for card insertion/removal
remains operable even with smart card clock disabled.
MCLKCtl.4
USBEN
1 = Disable the USB logic clock. This bit is not changed in PWRDN mode
but the function is disabled.
MCLKCtl.3
32KEN
1 = Disable the 32Khz oscillator. This function is not affected by PWRDN
mode. Note: This bit must be set if there is no 32KHz crystal or the 44 pin
package is used. Some internal clocks and circuits will not run if the
oscillator is enabled and no crystal is connected.
MCLKCtl.2
MCT.2
This value determines the ratio of the VCO frequency (MCLK) to the high-
speed crystal oscillator frequency such that:
MCLK = (MCount*2 + 4)*Fxtal. The default value is MCount = 2h such that
MCLK = (2*2 + 4)*12.00MHz = 96MHz.
MCLKCtl.1
MCT.1
MCLKCtl.0
MCT.0
*Note: The HSOEN bit should never be set under normal circumstances. Power down control should
only be initiated via use of the PWRDN bit in MISCtl0.
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