- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16696 > 73S1215F-EB-LITE (Maxim Integrated Products)BOARD EVAL 73S1215F CBL/DOC/CD PDF資料下載
參數(shù)資料
| 型號： | 73S1215F-EB-LITE |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 113/136頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL 73S1215F CBL/DOC/CD |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1 |
| 系列： | * |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁當前第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁
73S1215F Data Sheet
DS_1215F_003
78
Rev. 1.4
1.7.15.1 ISO 7816 UART
An embedded ISO 7816 (hardware) UART is provided to control communications between a smart card
and the 73S1215F MPU. The UART can be shared between the one built-in ICC interface and the
external ICC interface. Selection of the desired interface is made by register SCSel. Control of the
external interface is handled by the I
2C interface for any external 8010 devices. The following is a list of
features for the ISO 7816 UART:
Two-byte FIFO for temporary data storage on both TX and Rx data.
Parity checking in T=0. This feature can be enabled/disabled by firmware. Parity error reporting to
firmware and Break generation to ICC can be controlled independently.
Parity error generation for test purposes.
Retransmission of last byte if ICC indicates T=0 parity error. This feature can be enabled/disabled by
firmware.
Deletion of last byte received if ICC indicates T=0 parity error. This feature can be enabled/disabled
by firmware.
CRC/LRC generation and checking. CRC/LRC is automatically inserted into T=1 data stream by the
hardware. This feature can be enabled/disabled by firmware.
Support baud rates: 230000, 115200, 57600, 38400, 28800, 19200, 14400, 9600 under firmware
control (assuming 12MHz crystal) with various F/D settings
Firmware manages F/D. All F/D combinations are supported in which F/D is directly divisible by 31 or
32 (i.e. F/D is a multiple of either 31 or 32).
Flexible ETU clock generation and control.
Detection of convention (direct or indirect) character TS. This affects both polarity and order of bits in
byte. Convention can be overridden by firmware.
Supports WTX Timeout with an expanded Wait Time Counter (28 bits).
A Bypass Mode is provided to bypass the hardware UART in order for the software to emulate the
UART (for non-standard operating modes). In such a case, the I/O line value is reflected in SFR
some synchronous and non T=0 / T=1 cards.
The single integrated smart card UART is capable of supporting T=0 and T=1 cards in hardware
therefore offloading the bit manipulation tasks from the firmware. The embedded firmware instructs the
hardware which smart card it should communicate with at any point in time. Firmware reconfigures the
UART as required when switching between smart cards. When the 73S1215F has transmitted a
message with an expected response, the firmware should not switch the UART to another smart card
until the first smart card has responded. If the smart card responds while another smart card is selected,
that first smart card’s response will be ignored.
1.7.15.2 Answer to Reset Processing
A card insertion event generates an interrupt to the firmware, which is then responsible for the
configuration of the electrical interface, the UART and activation of the card. The activation sequencer
goes through the power up sequence as defined in the ISO 7816-3 specification. An asynchronous
activation timing diagram is shown in Figure 17. After the card RST is de-asserted, the firmware instructs
the hardware to look for a TS byte that begins the ATR response. If a response is not provided within the
pre-programmed timeout period, an interrupt is generated and the firmware can then take appropriate
action, including instructing the 73S1215F to begin a deactivation sequence. Once commanded, the
deactivation sequencer goes through the power down sequence as defined in the ISO 7816-3
specification. If an ATR response is received, the hardware looks for a TS byte that determines
direct/inverse convention. The hardware handles the indirect convention conversion such that the
embedded firmware only receives direct convention. This feature can be disabled by firmware within
SByteCtl register. Parity checking and break generation is performed on the TS byte unless disabled by
firmware. If during the card session, a card removal, over-current or other error event is detected, the
hardware will automatically perform the deactivation sequence and then generate an interrupt to the
firmware. The firmware can then perform any other error handling required for proper system operation.
相關PDF資料 |
PDF描述 |
|---|---|
| V375C48T75B2 | CONVERTER MOD DC/DC 48V 75W |
| RCC07DRAS-S734 | CONN EDGECARD 14POS .100 R/A PCB |
| ZRC400F01TC | IC VREF SHUNT PREC 4.096V SOT-23 |
| V72C12E150B2 | CONVERTER MOD DC/DC 12V 150W |
| H1AXS-2636G | IDC CABLE - HSC26S/AE26G/X |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 73S1217F | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Bus-Powered 80515 System-on-Chip with USB, ISO 7816 / EMV, PINpad and More |
| 73S1217F-68IM/F | 功能描述:8位微控制器 -MCU Bus Pwr’d 80515 SoC w/USB 7816/EMV PINpd RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| 73S1217F-68IM/F/P | 功能描述:IC SMART CARD READER PROG 68-QFN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:73S12xx 產(chǎn)品培訓模塊:MCU Product Line Introduction AVR® UC3 Introduction 標準包裝:2,500 系列:AVR®32 UC3 B 核心處理器:AVR 芯體尺寸:32-位 速度:60MHz 連通性:I²C，IrDA，SPI，SSC，UART/USART，USB 外圍設備:欠壓檢測/復位，DMA，POR，PWM，WDT 輸入/輸出數(shù):28 程序存儲器容量:128KB（128K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:32K x 8 電壓 - 電源 (Vcc/Vdd):1.65 V ~ 1.95 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 6x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TQFP 包裝:帶卷 (TR) 配用:ATSTK600-TQFP48-ND - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1101-ND - KIT DEV/EVAL FOR AVR32 AT32UC3B 其它名稱:AT32UC3B1128-AUR-NDAT32UC3B1128-AURTR |
| 73S1217F-68IMR/F | 功能描述:8位微控制器 -MCU Bus Pwr’d 80515 SoC w/USB 7816/EMV PINpd RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| 73S1217F-68IMR/F/P | 功能描述:IC SMART CARD READER PROG 68-QFN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:73S12xx 產(chǎn)品培訓模塊:MCU Product Line Introduction AVR® UC3 Introduction 標準包裝:2,500 系列:AVR®32 UC3 B 核心處理器:AVR 芯體尺寸:32-位 速度:60MHz 連通性:I²C，IrDA，SPI，SSC，UART/USART，USB 外圍設備:欠壓檢測/復位，DMA，POR，PWM，WDT 輸入/輸出數(shù):28 程序存儲器容量:128KB（128K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:32K x 8 電壓 - 電源 (Vcc/Vdd):1.65 V ~ 1.95 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 6x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TQFP 包裝:帶卷 (TR) 配用:ATSTK600-TQFP48-ND - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1101-ND - KIT DEV/EVAL FOR AVR32 AT32UC3B 其它名稱:AT32UC3B1128-AUR-NDAT32UC3B1128-AURTR |
發(fā)布緊急采購，3分鐘左右您將得到回復。