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參數(shù)資料
型號(hào): 73S1215F-EB-LITE
廠商: Maxim Integrated Products
文件頁數(shù): 20/136頁
文件大?。?/td> 0K
描述: BOARD EVAL 73S1215F CBL/DOC/CD
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
系列: *
73S1215F Data Sheet
DS_1215F_003
116
Rev. 1.4
Parameter
Condition
Min
Typ.
Max
Unit
CL = 50pf, series 24Ω, 1% source termination resistor included
Rise Time
USBTR
10% to 90%
4
20
ns
Fall Time
USBTF
90% to 10%
4
20
ns
Rise/fall time matching
TRFM
(USBTR/USBTF)
90
111.11
%
Output signal crossover
voltage
VCRS
Includes VDI range
1.3
2.0
V
Source Jitter to Next
Transition
TDJ1
Measured as in Figure
7-49 of USB 2.0 Spec
-3.5
3.5
ns
Source Jitter For Paired
Transitions
TDJ2
Measured as in Figure 7-
49 of USB 2.0 Spec (1) (2)
-4
4
ns
Receiver Jitter to Next
Transition
TJR1
Measure as in Figure 7-51
of USB 2.0 Spec.
Characterized but not
production tested.
-18.5
18.5
ns
Receiver Jitter for Paired
Transitions
TJR2
Measure as in Figure 7-51
of USB 2.0 Spec.
Characterized but not
production tested.
-9
9
ns
Source SE0 interval of
EOP
TEOPT
Figure 7-50 of USB 2.0
Spec
160
175
ns
Receiver SEO interval of
EOP
TEOPR
Figure 7-50 of USB 2.0
Spec. (3)
82
ns
(1) For both transitions of differential signaling.
(2) Excluding first transition from the Idle state.
(3) Must accept as valid EOP.
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