參數(shù)資料
型號: 7641
英文描述: 7641 Group Datasheet Datasheet 2145K/MAR.26.02
中文描述: 7641組數(shù)據(jù)表數(shù)據(jù)表2145K/MAR.26.02
文件頁數(shù): 131/137頁
文件大小: 2145K
代理商: 7641
130
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
USB
When the USB Reset Interrupt Status Flag is kept at “1”, all other
flags in the USB internal registers (addresses 0050
16
to 005F
16
)
will return to their reset status. However, the following registers
are not affected by the USB reset: USB control register (address
0013
16
), Frequency synthesizer control register (address
006C
16
), Clock control register (address 001F
16
), and USB end-
point-x FIFO register (addresses 0060
16
to 0064
16
).
When not using the USB function, set the USB Line Driver Supply
Enable Bit of the USB control register (address 0013
16
) to “1” for
power supply to the internal circuits (at Vcc = 5V).
When using an isochronous transfer, set the FLUSH Bit (bit 6 of
address 0059
16
and bit 6 of address 005A
16
) as follows:
IN FIFO: use AUTO_FLUSH Bit (bit 6 of 0058
16
)
OUT FIFO: when OUT_PKT_RDY Bit is “1”, set FLUSH Bit to “1”
When the USB SOF Port Select Bit is “1”, the reference pulse of
83.3 ns (
φ
= 12 MHz) is output from the P7
0
/SOF pin and syn-
chronized with the SOF packet.
If a character bit length is 7 bits, bit 7 of the UARTx transmit/re-
ceive buffer register 1 and bits 0 to 7 of the UARTx transmit/
receive buffer register 2 are ignored at transmitting; they are in-
valid at receiving.
If a character bit length is 8 bits, bits 0 to 7 of the UARTx transmit/
receive buffer register 2 are ignored at transmitting; they are in-
valid at receiving.
If a character bit length is 9 bits, bits 1 to 7 of the UARTx transmit/
receive buffer register 2 are ignored at transmitting; they are “0”
at receiving.
The IN_PKT_RDY Bit can be set by software even when using
the AUTO_SET function.
When writing to USB-related registers, set the USB Clock Enable
Bit to “1”, then perform the write after four
φ
cycle waits.
When using the MCU at Vcc = 3.3V, set the USB Line Driver Sup-
ply Enable Bit to “0” (line driver disable). Note that setting the
USB Line Driver Current Control Bit (USBC3) doesn’t affect the
USB operation.
Read one packet data from the OUT FIFO before clearing the
OUT_PKT_RDY Flag. If the OUT_PKT_RDY Flag is cleared
while one packet data is being read, the internal read pointer can-
not operate normally.
Use the transfer instructions such as
LDA
and
STA
to set the reg-
isters: USB interrupt status registers 1, 2 (addresses 0052
16
,
0053
16
); USB endpoint 0 IN control register (address 0059
16
);
USB endpoint x IN control register (address 0059
16
); USB end-
point x OUT control register (address 005A
16
). Do not use the
read-modify-write instructions such as the
SEB
or the
CLB
in-
struction.
When writing to bits shown by Table 32 using the transfer instruc-
tion such as
LDA
or
STA
, a value which never affect its bit state
is required. Take the following sequence to change these bits
contents:
(1) Store the register contents onto a variable or a data register.
(2) Change the target bit on the variable or the data register. Si-
multaneously mask the bit so that its bit state cannot be
changed. (See to Table 39.)
(3) Write the value from the variable or the data register to the
register using the transfer instruction such as
LDA
or
STA.
Table 32 Bits of which state might be changed owing to software write
Register name
USB endpoint 0 IN control register
USB endpoint x (x = 1 to 4) IN control register
USB endpoint x (x = 1 to 4) OUT control register
Bit name
IN_PKT_RDY (b1)
DATA_END (b3)
FORCE_STALL (b4)
IN_PKT_RDY (b0)
UNDER_RUN (b1)
OUT_PKT_RDY (b0)
OVER_RUN (b1)
FORCE_STALL (b4)
DATA_ERR (b5)
Value not affecting state (
Note
)
“0”
“0”
“1”
“0”
“1”
“1”
“1”
“1”
“1”
Note:
Writing this value will not change the bit state, because this value cannot be written to the bit by software.
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