參數(shù)資料
型號： 7641
英文描述： 7641 Group Datasheet Datasheet 2145K/MAR.26.02
中文描述： 7641組數(shù)據(jù)表數(shù)據(jù)表2145K/MAR.26.02
文件頁數(shù)： 22/137頁
文件大?。?/td> 2145K
代理商： 7641
21
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7641 Group
Interrupt Source
Reset
(Note 3)
USB function
USB SOF
INT
0
INT
1
DMAC0
DMAC1
UART1 receive
buffer full
UART1 transmit
UART1
summing error
UART2 receive
buffer full
UART2 transmit
UART2
summing error
Timer X
Timer Y
Timer 1
Timer 2
Timer 3
CNTR
0
CNTR
1
Serial I/O
Input buffer full
Output buffer
empty
Key input (Key-
on wake-up)
BRK instruction
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Vector Addresses
(Note 1)
High
FFFB
16
FFF9
16
FFF7
16
FFF5
16
FFF3
16
FFF1
16
FFEF
16
FFED
16
FFEB
16
FFE9
16
FFE7
16
FFE5
16
FFE3
16
FFE1
16
FFDF
16
FFDD
16
FFDB
16
FFD9
16
FFD7
16
FFD5
16
FFD3
16
FFD1
16
FFCF
16
FFCD
16
FFCB
16
Interrupt Request
Generating Conditions
At reset
(
Note 2
)
At reception of SOF packet
At detection of either rising or falling edge of
INT
0
intput
At detection of either rising or falling edge of
INT
1
input
At completion of DMAC0 transfer
At completion of DMAC1 transfer
At completion of UART1 reception
At completion of UART1 transmission
At detection of UART1 summing error
At completion of UART2 reception
At completion of UART2 transmission
At detection of UART2 summing error
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At timer 3 underflow
At detection of either rising or falling edge of
CNTR
0
input
At detection of either rising or falling edge of
CNTR
1
input
At completion of serial I/O transmission/re-
ception
At writing to input data bus buffer
At reading from output data bus buffer
At falling of port P2 input logical level AND
At BRK instruction execution
Remarks
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Low
FFFA
16
FFF8
16
FFF6
16
FFF4
16
FFF2
16
FFF0
16
FFEE
16
FFEC
16
FFEA
16
FFE8
16
FFE6
16
FFE4
16
FFE2
16
FFE0
16
FFDE
16
FFDC
16
FFDA
16
FFD8
16
FFD6
16
FFD4
16
FFD2
16
FFD0
16
FFCE
16
FFCC
16
FFCA
16
Notes 1
: Vector addresses contain interrupt jump destination addresses.
2
: USB function interrupt occurs owing to an interrupt request of the endpoint x (x = 0 to 4) IN, endpoint x OUT, overrun/underrun, USB reset or suspend/
resume.
3
: Reset functions in the same way as an interrupt with the highest priority.
Table 7 Interrupt vector addresses and priority
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(falling valid)
Non-maskable software interrupt
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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