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參數(shù)資料
| 型號(hào)： | 7641 |
| 英文描述： | 7641 Group Datasheet Datasheet 2145K/MAR.26.02 |
| 中文描述： | 7641組數(shù)據(jù)表數(shù)據(jù)表2145K/MAR.26.02 |
| 文件頁(yè)數(shù)： | 67/137頁(yè) |
| 文件大小： | 2145K |
| 代理商： | 7641 |
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66
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
FREQUENCY SYNTHESIZER (PLL)
The frequency synthesizer generates the 48 MHz clock required
by f
USB
and f
SYN
, which are multiples of the external input refer-
ence f(X
IN
). Figure 59 shows the block diagram for the frequency
synthesizer circuit.
The Frequency Synthesizer Input Bit selects either f(X
IN
) or
f(X
CIN
) as an input clock f
IN
for the frequency synthesizer.
The Frequency Synthesizer Multiply Register 2 (FSM2: address
006E
16
) divides f
IN
to generate f
PIN
, where
f
PIN
= f
IN
/ 2(n + 1), n: value set to FSM2.
When the value of Frequency Synthesizer Multiply Register 2 is
set to 255, the division is not performed and f
PIN
will equal f
IN
.
f
VCO
is generated according to the contents of Frequency Synthe-
sizer Multiply Register 1 (FSM1: address 006D
16
), where
f
VCO
= f
PIN
{2(n + 1)}, n: value set to FSM1.
Set the value of FSM1 so that the value of f
VCO
is 48 MHz.
f
SYN
is generated according to the contents of the Frequency Syn-
thesizer Divide Register (FSD: address 006F
16
), where
f
SYN
= f
VCO
/ 2(m + 1), m: value set to FSD.
When the value of the Frequency Synthesizer Divide Register is
set to 255, the division is not performed and f
SYN
becomes invalid.
[Frequency Synthesizer Control Register] FSC
Setting the Frequency Synthesizer Enable Bit (FSE) to
“
1
”
enables
the frequency synthesizer. When the Frequency Synthesizer Lock
Status Bit (LS) is
“
1
”
in the frequency synthesizer enabled, this in-
dicates that f
SYN
and f
VCO
have correct frequencies.
I
Notes
Make sure to connect a low-pulse filter to the LPF pin when using
the frequency synthesizer. In addition, please refer to
“
Program-
ming Notes: Frequency Synthesizer
”
when recovering from a
Hardware Reset.
FSM2
D
a
t
a
B
u
s
FSM1
FSC
Prescaler
f
IN
f
PIN
f
VCO
f
SYN
f
U
S
B
(a
d
d
r
e
s
s
0
0
6
E
1
6
)
(address 006D
16
)
(a
d
d
r
e
s
s
0
0
6
C
1
6
)
(a
d
d
r
e
s
s
0
0
6
F
1
6
)
FSD
Frequency
Multiplier
Frequency Divider
F
e
r
q
u
e
n
c
y
s
y
n
t
h
e
s
i
z
e
r
l
o
c
k
s
t
t
u
s
b
i
t
Fig. 59 Frequency synthesizer block diagram
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