參數資料
型號： 7641
英文描述： 7641 Group Datasheet Datasheet 2145K/MAR.26.02
中文描述： 7641組數據表數據表2145K/MAR.26.02
文件頁數： 43/137頁
文件大?。?/td> 2145K
代理商： 7641
42
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
(2) Burst Transfer Mode
When the DMAC Channel x Transfer Mode Selection Bit (DxTMS)
is set to
“
1
”
, the respective DMAC channel operates in the burst
transfer mode.
In the burst transfer mode, the DMAC continually transfers the
number of bytes of data specified by the Transfer Count Register
for one transfer request. Other than this, the burst transfer mode
operation is the same as the cycle steal mode operation.
Priority
The DMAC places a higher priority on Channel-0 transfer requests
than on Channel-1 transfer requests.
If a Channel-0 transfer request occurs during a Channel-1 burst
transfer operation, the DMAC completes the next transfer source
and destination read/write operation first, and then starts the
Channel-0 transfer operation. As soon as the Channel-0 transfer is
completed, the DMAC resumes the Channel-1 transfer operation.
When an interrupt request occurs during any DMA operation, the
transfer operation is suspended and the interrupt process routine
is initiated. During the interrupt operation, the DMAC automatically
sets the corresponding DMAC Channel x (x = 0, 1) Suspend Flag
(DxSFI) to
“
1
”
. As soon as the CPU completes the interrupt opera-
tion, the DMAC clears the flag to
“
0
”
and resumes the original
operation from the point where it was suspended.
The suspended transfer due to the interrupt can also be resumed
during its interrupt process routine by writing
“
1
”
to the DMAC
Channel x (x = 0,1) Enable Bit (DxCEN).
The timing charts for a burst transfer caused by a hardware-re-
lated transfer request are shown in Figure 35.
Fig. 35 Timing chart for burst transfer caused by hardware-related transfer request
A5
AD
L
1
85
PC + 2
AD
L
1, 00
PC + 1
PC
PC + 3
LDA $zz
STA $zz
(First cycle)
STA $zz
(Second cycle)
φ
O
U
T
S
Y
N
C
O
U
T
R
D
WR
D
P
e
r
(
“
L
M
o
r
r
e
”
A
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t
P
q
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(
3
3
)
e
s
v
e
Address
Data
T
o
r
a
r
n
c
s
f
t
)
s
u
e
t
i
Transfer request source
sampling
e
r
r
e
q
e
s
a
m
R
e
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e
t
o
f
s
t
r
o
a
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n
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s
c
f
u
p
e
i
n
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g
t
l
DMA transfer
Data
D
t
i
M
o
A
d
d
e
d
s
.
t
1
i
n
a
-
n
a
D
M
A
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.
u
1
r
c
e
d
D
t
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M
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A
d
d
e
d
s
.
t
2
i
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a
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A
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s
d
o
.
u
2
r
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d
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d
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t
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A
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1
D
d
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A
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1
D
d
M
t
a
A
a
2
DMA
data 2
A
D
L
2
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