參數(shù)資料
型號： 7641
英文描述： 7641 Group Datasheet Datasheet 2145K/MAR.26.02
中文描述： 7641組數(shù)據(jù)表數(shù)據(jù)表2145K/MAR.26.02
文件頁數(shù)： 60/137頁
文件大小： 2145K
代理商： 7641
59
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 54 Interrupt request circuit of data bus buffer
MASTER CPU BUS INTERFACE
The 7641 group internally has a 2-byte bus interface which control
signals from the host CPU side can operate (slave mode).
This bus interface allows the 7641 group to be directly connected
with a R/W type of CPU bus or a RD and WR separated type of
CPU bus. Figure 56 shows the block diagram of master CPU bus
interface function.
The data bus buffer function I/O pins (P5
2
– P5
7
, P6, P7
2
–P7
4
)
also function as the normal I/O ports. When the Master CPU Bus
Interface Enable bit of Data Bus Buffer Control Register (bit 6 of
address 004A
16
) is “0”, these pins become the normal I/O ports.
When it is “1”, these pins become the master CPU bus interface
function pins.
Additionally, when using the master CPU bus interface function,
set port P6 to input mode by setting “00
16
” into its port direction
register (address 0015
16
).
The selection of either the single data bus buffer mode, which
uses 1 byte: data bus buffer 0 only, or the double data bus buffer
mode, which uses 2 bytes: data bus buffer 0 and data bus buffer
1, is performed by the Data Bus Buffer Function Select Bit of Data
Bus Buffer Control Register 1 (bit 7 of address 004E
16
). Port P7
2
becomes S
1
input pin in the double data bus buffer mode.
When data is written from the host CPU side, an input buffer full
interrupt occurs. When data is read from the host CPU, an output
buffer empty interrupt occurs. The 7641 group shares two input
buffer full interrupt requests and two output buffer empty interrupt
requests as shown in Figure 54, respectively.
The 7641 group can also operate the master CPU bus interface
connecting with the Built-in DMAC. This could transfer a large
amount of data fast.
An input signal level of data bus buffer function input pins can be
selected between a CMOS level and a TTL level. Set it using the
Master CPU Bus Input Level Select Bit of Port Control Register
(address 0010
16
)
.
In
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0
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0
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1
Rising edge
detection circuit
One-shot pulse
generating circuit
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Input buffer full interrupt
request signal IBF
Output buffer
full flag 0 OBF
0
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1
One-shot pulse
generating circuit
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Output buffer empty interrupt
request signal OBE
Interrupt request is set at this rising edge
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)
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1
Rising edge
detection circuit
Rising edge
detection circuit
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