2009 Teridian Semiconductor Corporation Rev 1.3 MR17" />
參數(shù)資料
型號(hào): 78Q2120C09-64CGTR/F
廠商: Maxim Integrated Products
文件頁數(shù): 10/35頁
文件大?。?/td> 0K
描述: TXRX 10/100 BASE 3.3V 64-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1,500
類型: 以太網(wǎng)
驅(qū)動(dòng)器/接收器數(shù): 4/4
規(guī)程: MII
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 帶卷 (TR)
78Q2120C
10/100BASE-TX
Transceiver
Page: 18 of 35
2009 Teridian Semiconductor Corporation
Rev 1.3
MR17: Interrupt Control/Status Register (continued)
BIT
SYMBOL
TYPE DEFAULT DESCRIPTION
17.3
LP-ACK_INT
RC
0
Link Partner Acknowledge Interrupt: This bit is set high by the
auto-negotiation logic when FLP bursts are received with the
acknowledge bit set.
17.2
LS_CHG_INT
RC
0
Link Status Change Interrupt:
This bit is set when the link
transitions from an OK status to a FAIL status.
17.1
RFAULT_INT
RC
0
Remote Fault Interrupt:
This bit is set when a remote fault
condition has been indicated by the link partner.
17.0
ANEG-
COMP_INT
RC
0
Auto-Negotiation Complete Interrupt: This bit is set by the auto-
negotiation logic upon successful completion of auto-negotiation.
MR18: Diagnostic Register
BIT
SYMBOL TYPE DEFAULT DESCRIPTION
18.15:13
RSVD
R
00h
Reserved: Must set to ‘00h’.
18.12
ANEGF
RC
0
Auto-Negotiation Fail Indication:
This bit is set when auto-
negotiation completes and no common technology was found. It
remains set until read.
18.11
DPLX
R
0
Duplex Indication:
This bit indicates the result of the auto-
negotiation for duplex arbitration as follows:
0 : Half-duplex was the highest common denominator
1 : Full-duplex was the highest common denominator
18.10
RATE
R
0
Rate Indication: This bit indicates the result of the auto-negotiation
for data rate arbitration as follows:
0 : 10Base-T was the highest common denominator
1 : 100Base-TX was the highest common denominator
18.9
RXSD
R
0
Receiver Signal Detect Indication:
In 10Base-T mode, this bit
indicates that Manchester data has been detected. In 100Base-TX
mode, it indicates that the receive signal activity has been detected
(but not necessarily locked on to).
18.8
RX_LOCK
R
0
Receive PLL Lock Indication: Indicates that the Receive PLL has
locked onto the receive signal for the selected speed of operation
(10Base-T or 100Base-TX).
18.7:0
RSVD
R
00h
Reserved: Must set to ‘00h’.
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