2009 Teridian Semiconductor Corporation Rev 1.3 MR1:" />
參數(shù)資料
型號(hào): 78Q2120C09-64CGTR/F
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 5/35頁(yè)
文件大?。?/td> 0K
描述: TXRX 10/100 BASE 3.3V 64-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1,500
類型: 以太網(wǎng)
驅(qū)動(dòng)器/接收器數(shù): 4/4
規(guī)程: MII
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 帶卷 (TR)
78Q2120C
10/100BASE-TX
Transceiver
Page: 13 of 35
2009 Teridian Semiconductor Corporation
Rev 1.3
MR1: Status Register
BIT
SYMBOL TYPE DEFAULT DESCRIPTION
1.9
100T2_H
R
0
100BASE-T2 Half Duplex Ability:
Reads ‘0’ to indicate the
78Q2120C does not support 100Base-T2 full duplex mode.
1.8
EXTS
R
0
Extended Status Information Availability: Reads ‘0’ to indicate the
78Q2120C does not support Extended Status information on MR15.
1.7
RSVD
R
0
Reserved
1.6
MFPS
R
0
Management Frame Preamble Suppression Support:
A “0”
indicates that the 78Q2120C can read management frames with a
preamble.
1.5
ANEGC
R
0
Auto-Negotiation Complete: A logic one indicates that the Auto-
Negotiation process has been completed, and that the contents of
registers MR4,5,6 are valid.
1.4
RFAULT
RC
0
Remote Fault: A logic one indicates that a remote fault condition
has been detected and remains set until it is cleared. This bit can
only be cleared by reading this register (MR1) via the management
interface.
1.3
ANEGA
R
(1)
Auto-Negotiation Ability: When set, this bit indicates the device’s
ability to perform Auto-Negotiation.
The value of this bit is
determined by the ANEGEN bit (MR0.12).
1.2
LINK
R
0
Link Status:
A logic one indicates that a valid link has been
established. If the link status should transition from an OK status to
a NOT-OK status, this bit will become cleared and remains cleared
until it is read.
1.1
JAB
RC
0
Jabber Detect: In 10Base-T mode, this bit is set during a jabber
event. After a jabber event, the bit remains set until cleared by a
read operation.
1.0
EXTD
R
1
Extended Capability: Reads ’1’ to indicate the 78Q2120C provides
an extended register set (MR2 and beyond).
MR2: PHY Identifier Register 1
BIT
SYMBOL TYPE
VALUE
DESCRIPTION
2.15:0
OUI
[23:6]
R
000Eh
Organizationally Unique Identifier:
This value is 00-C0-39 for
TERIDIAN Semiconductor Corporation. This register contains the
first 16-bits of the identifier.
MR3: PHY Identifier Register 2
BIT
SYMBOL TYPE
VALUE
DESCRIPTION
3.15:10
OUI
[5:0]
R
1Ch
Organizationally Unique Identifier: Remaining 6 bits of the OUI.
3.9:4
MN
R
0Ch
Model Number: The last 2 digits of the model number 78Q2120C are
encoded into the 6 bits.
3.3:0
RN
R
9h
Revision Number: The value ‘1001’ corresponds to the ninth revision
of the silicon.
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