2009 Teridian Semiconductor Corporation Rev 1.3 100B" />
參數(shù)資料
型號(hào): 78Q2120C09-64CGTR/F
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 19/35頁(yè)
文件大?。?/td> 0K
描述: TXRX 10/100 BASE 3.3V 64-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1,500
類型: 以太網(wǎng)
驅(qū)動(dòng)器/接收器數(shù): 4/4
規(guī)程: MII
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 帶卷 (TR)
78Q2120C
10/100BASE-TX
Transceiver
Page: 26 of 35
2009 Teridian Semiconductor Corporation
Rev 1.3
100BASE-TX System Timing
System timing requirements for 100BASE-TX operation are listed in Table 24-2 of Clause 24 of IEEE 802.3.
PARAMETER
CONDITION
NOM
UNIT
TX_EN Sampled to first bit of “J” on MDI
output
12
BT
First bit of “J” on MDI input to CRS assert
16
BT
First bit of “T” on MDI input to CRS
de-assert
23
BT
First bit of “J” on MDI input to COL assert
20
BT
First bit of “T” on MDI input to COL
de-assert
24
BT
TX_EN Sampled to CRS assert
RPTR = low
6
BT
TX_EN sampled to CRS de-assert
RPTR = low
6
BT
10BASE-T System Timing
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
TX_EN (MII) to TD Delay
6
BT
RD to RXD at (MII) Delay
6
BT
Collision delay
9
BT
SQE test wait
1
s
SQE test duration
1
s
Jabber on-time*
20
150
ms
Jabber off-time*
250
750
ms
* Guarantee by design. The specifications in the following table are included for information only.
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