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SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Table 3. 80960CF Pin DescriptionDProcessor Control Signals
(Continued)
Name
Type
Description
STEST
I
SELF TEST
causes the processor’s internal self-test feature to be enabled or
disabled at initialization. STEST is read on the rising edge of RESET. When asserted,
the processor’s internal self-test and external bus confidence tests are performed
during processor initialization. When deasserted, only the external bus confidence
tests are performed during initialization.
S(L)
H(Z)
R(Z)
ONCE
I
ON CIRCUIT EMULATION
causes all outputs to be floated when asserted. ONCE is
continuously sampled while RESET is low, and is latched on the rising edge of
RESET. To place the processor in the ONCE state:
(1)
assert RESET and ONCE (order does not matter)
(2)
wait for at least 16 CLKIN periods in 2-x mode, or 10,000 CLKIN periods in 1-x
mode, after V
CC
and CLKIN are within operating specifications
(3)
deassert RESET
(4)
wait at least 32 CLKIN periods
(The processor is now latched in the ONCE state as long as RESET is high.)
A(L)
H(Z)
R(Z)
To exit the ONCE state, bring V
CC
and CLKIN to operating conditions, then assert
RESET and bring ONCE high prior to deasserting RESET.
CLKIN must operate within the specified operating conditions of the processor until
step 4 above is completed. The CLKIN may then be changed to DC to achieve the
lowest possible ONCE mode leakage current.
ONCE can be used by emulator products or for board testers to effectively make an
installed processor transparent in the board.
CLKIN
I
CLOCK INPUT
is an input for the external clock needed to run the processor. The
external clock is internally divided as prescribed by the CLKMODE pin to produce
PCLK2:1.
A(E)
H(Z)
R(Z)
CLKMODE
I
CLOCK MODE
selects the division factor applied to the external clock input (CLKIN).
When CLKMODE is high, CLKIN is divided by one to create PCLK2:1 and the
processor’s internal clock. When CLKMODE is low, CLKIN is divided by two to create
PCLK2:1 and the processor’s internal clock. CLKMODE should be tied high or low in
a system, as the clock mode is not latched by the processor. If left unconnected, the
processor internally pulls the CLKMODE pin low, enabling the 2-x clock mode.
A(L)
H(Z)
R(Z)
PCLK2
PCLK1
O
S
PROCESSOR OUTPUT CLOCKS
provide a timing reference for all inputs and
outputs of the processor. All inputs and output timings are specified in relation to
PCLK2 and PCLK1. PCLK2 and PCLK1 are identical signals. Two output pins are
provided to allow flexibility in the system’s allocation of capacitive loading on the
clock. PCLK2:1 may also be connected at the processor to form a single clock signal.
H(Q)
R(Q)
V
SS
D
GROUND
connections consist of 24 pins which must be connected externally to a
V
SS
board plane.
V
CC
D
POWER
connections consist of 24 pins which must be connected externally to a V
CC
board plane.
V
CCPLL
D
V
CCPLL
is a separate V
CC
supply pin for the phase lock loop used in 1x clock mode.
Connecting a simple low pass filter to V
CCPLL
may help reduce clock jitter (T
CP
) in
noisy environments. Otherwise, V
CCPLL
should be connected to V
CC
.
N/C
D
NO CONNECT
pins must not be connected in a system.
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