參數(shù)資料
型號(hào): 80960CF
廠商: Intel Corp.
英文描述: 32-Bit High-Performance Superscalar Processor(32位高性能超標(biāo)量處理器)
中文描述: 32位高性能超標(biāo)量處理器(32位高性能超標(biāo)量處理器)
文件頁數(shù): 13/62頁
文件大?。?/td> 999K
代理商: 80960CF
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Table 4. 80960CF Pin DescriptionDDMA and Interrupt Unit Control Signals
Name
Type
Description
DREQ3
DREQ2
DREQ1
DREQ0
I
DMA REQUEST
causes a DMA transfer to be requested. Each of the four signals
request a transfer on a single channel. DREQ0 requests channel 0, DREQ1 requests
channel 1, etc. When two or more channels are requested simultaneously, the
channel with the highest priority is serviced first. Channel priority mode is
programmable.
A(L)
H(Z)
R(Z)
DACK3
DACK2
DACK1
DACK0
O
S
DMA ACKNOWLEDGE
indicates that a DMA transfer is being executed. Each of the
four signals acknowledge a transfer for a single channel. DACK0 acknowledges
channel 0, DACK1 acknowledges channel 1, etc. DACK3:0 are asserted when the
requesting device of a DMA is accessed.
H(1)
R(1)
EOP3/TC3
EOP2/TC2
EOP1/TC1
EOP0/TC0
I / O
A(L)
H(Z/Q)
R(Z)
END OF PROCESS/TERMINAL COUNT
can be programmed as either an input
(EOP3:0) or as an output (TC3:0), but not both. Each pin is individually
programmable. When programmed as an input, EOPx causes the termination of a
current DMA transfer for the channel corresponding to the EOPx pin. EOP0
corresponds to channel 0, EOP1 corresponds to channel 1, etc. When a channel is
configured for sourceand destination chaining, the EOP pin for that channel causes
termination of only the current buffer transferred and causes the next buffer to be
transferred. EOP3:0 are asynchronous inputs.
When programmed as an output, the channel’s TCx pin indicates that the channel
byte count has reached 0 and a DMA has terminated. TCx is driven with the same
timing as DACKx during the last DMA transfer for a buffer. If the last bus request is
executed as multiple bus accesses, TCx remains asserted for the entire bus request.
XINT7
XINT6
XINT5
XINT4
XINT3
XINT2
XINT1
XINT0
I
EXTERNAL INTERRUPT PINS
cause interrupts to be requested. These pins can be
configured in three modes.
In Dedicated Mode, each pin is a dedicated external interrupt source. Dedicated
inputs can be individually programmed to be level (low) or edge (falling) activated.
In Expanded Mode, the 8 pins act together as an 8-bit vectored interrupt source. The
interrupt pins in this mode are level activated. Since the interrupt pins are active low,
the vector number requested is the one’s complement of the positive logic value
place on the port. This eliminates glue logic to interface to combinational priority
encoders which output negative logic.
In Mixed Mode, XINT7:5 are dedicated sources and XINT4:0 act as the 5 most
significant bits of an expanded mode vector. The least significant bits are set to 010
internally.
A(E/L)
H(Z)
R(Z)
NMI
I
NON-MASKABLE INTERRUPT
causes a non-maskable interrupt event to occur.
NMI is the highest priority interrupt recognized. NMI is an edge (falling) activated
source.
A(E)
H(Z)
R(Z)
13
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80960CF-30 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:SPECIAL ENVIRONMENT 80960CF-30, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR
80960CF-33 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR
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