參數(shù)資料
型號(hào)： 80960RN
廠商： Intel Corp.
英文描述： 80960RN I/O Processor(80960RN I/O 處理器)
中文描述： 80960RN I / O處理器（80960RN的I / O處理器）
文件頁(yè)數(shù)： 17/54頁(yè)
文件大小： 851K
代理商： 80960RN
Data Sheet
—
80960RN
Advance Information
17
Table 4.
Memory Controller Signals (Sheet 1 of 3)
NAME
COUNT
TYPE
DESCRIPTION
DCLKOUT
1
O
Irst(Q)
SDRAM OUTPUT CLOCK
dedicated for SDRAM memory
subsystem.
DCLKIN
1
I
SDRAM INPUT CLOCK
dedicated for SDRAM memory
subsystem. Used to skew DCLKOUT appropriately to
accommodate flight time and clock buffer delays.
SA[11:0]
12
O
Irst(Q)
SDRAM MULTIPLEXED ADDRESS BUS
carries the multiplexed
row and column addresses to the SDRAM memory banks. For
SA[10]
, see note 1.
SBA[1:0]
2
O
Irst(Q)
SDRAM INTERNAL BANK SELECT
indicates which of the SDRAM
internal banks are read or written during the current transaction.
SRAS#
1
O
Irst(1)
SDRAM ROW ADDRESS STROBE
indicates the presence of a valid
row address on the Multiplexed Address Bus
SA[11:0]
. See note 1.
SCAS#
1
O
Irst(1)
SDRAM COLUMN ADDRESS STROBE
indicates the presence of
a valid column address on the Multiplexed Address Bus
SA[11:0]
.
See note 1.
SDQM[7:0]
8
O
Irst(1)
SDRAM DATA MASK
controls which of the eight bytes on the data
bus should be written or read. When
SDQM[7:0]
asserted, the
SDRAM devices do not accept/drive valid data from/to the byte
lanes. When
SDQM[7:0]
deasserted, the SDRAM devices
accept/drive valid data from/to the byte lanes.
By convention, SDQM[1] masks two x8 SDRAM devices.
Functionally, all
SDQM[7:0]
signals are equivalent.
SWE#
1
O
Irst(1)
SDRAM WRITE ENABLE
indicates that the current memory
transaction is a write operation. See note 1.
SCE[1:0]#
2
O
Irst(1)
SDRAM CHIP ENABLE
enables the SDRAM devices for a
memory access (1 per bank supported). See note 1.
SCKE[1:0]
2
O
Irst(Q)
SCKE[1:0]
are the clock enables for the SDRAM memory.
Deasserting will place the SDRAM in self-refresh mode. See note 1.
DQ[63:0]
64
I/O
Irst(1)
Sync(D)
DATA BUS
carries 64-bit data to and from memory. During a data
(T
d
) cycle, read or write data is present on one or more contiguous
bytes, comprising DQ[63:56], DQ[55:48], DQ[47:40], DQ[39:32],
DQ[31:24], DQ[23:16], DQ[15:8] and DQ[7:0]. During write
operations, unused pins are driven to determinate values.
SCB[7:0]
8
I/O
Irst(1)
Sync(D)
ERROR CORRECTION CODE
carries the 8-bit ECC code to and
from memory during data cycles.
ROE#
1
O
Irst(1)
ROM OUTPUT ENABLE
specifies, during a T
a
cycle, whether the
operation is a write (1) or read (0) to the ROM interface. It remains
valid during T
d
cycles. When
ROE#
is asserted, the data is
transferred from the memory on
RAD[16:9]
.
RWE#
1
O
Irst(1)
ROM WRITE ENABLE
indicates the direction data is to be
transferred to/from ROM and controls the WE input on the ROM
device. When
RWE#
is asserted, the data is transferred to the
memory on DQ[7:0].
RCE[1:0]#
2
O
Irst(1)
FLASH CHIP ENABLE
enables Flash devices for a memory access.
RALE
1
O
Irst(0)
ROM ADDRESS LATCH ENABLE
indicates the cycle in which the
address on RAD[16:3] should be externally latched for the Flash
subsystem.
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