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參數(shù)資料
| 型號： | 80960RN |
| 廠商： | Intel Corp. |
| 英文描述： | 80960RN I/O Processor(80960RN I/O 處理器) |
| 中文描述： | 80960RN I / O處理器（80960RN的I / O處理器） |
| 文件頁數(shù)： | 43/54頁 |
| 文件大?。?/td> | 851K |
| 代理商： | 80960RN |
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Data Sheet
—
80960RN
Advance Information
43
4.2
VCC5REF
Pin Requirements (V
DIFF
)
In mixed voltage systems that drive 80960RN processor inputs in excess of 3.3 V, the
VCC5REF
pin must be connected to the system
’
s 5 V supply. To limit current flow into the
VCC5REF
pin,
there is a limit to the voltage differential between the
VCC5REF
pin and the other V
CC
pins. The
voltage differential between the
VCC5REF
pin and its 3.3 V V
CC
pins should never exceed
2.25 V. This limit applies to power-up, power-down, and steady-state operation.
Table 20
outlines
this requirement.
If the voltage difference requirements cannot be met due to system design limitations, an alternate
solution may be employed. As shown in
Figure 6
, a minimum of 100
series resistor may be used
to limit the current into the
VCC5REF
pin. This resistor ensures that current drawn by the
VCC5REF
pin does not exceed the maximum rating for this pin.
This resistor is not necessary in systems that can guarantee the V
DIFF
specification.
In 3.3 V-only systems (only applies to 80960RN C-x steppings) and systems that drive pins from
3.3 V logic, connect the
VCC5REF
pin directly to the 3.3 V V
CC
plane.
4.3
V
CCPLL
Pin Requirements
To reduce clock skew on the i960 Jx processor, the V
CCPLL
pin for the Phase Lock Loop (PLL)
circuit is isolated on the pinout. The lowpass filter, as shown in
Figure 7
, reduces noise induced
clock jitter and its effects on timing relationships in system designs. The 4.7 μF capacitor must be
(low ESR solid tantalum), the 0.01 μF capacitor must be of the type X7R and the node connecting
V
CCPLL
must be as short as possible.
Figure 6.
VCC5REF Current-Limiting Resistor
+5 V (±0.25 V)
VCC5REF Pin
100
(±5%, 0.5 W)
Table 20.
V
DIFF
Specification for Dual Power Supply Requirements (3.3 V, 5 V)
Symbol
Parameter
Min
Max
Units
Notes
V
DIFF
V
CC5
-V
CC
Difference
2.25
V
(1)
NOTE:
1.
VCC5REF
input should not exceed V
CC
by more than 2.25 V during power-up and power-down, or during
steady-state operation.
Figure 7.
V
CCPLL
Lowpass Filter
10
, 5%, 1/8W
V
CC
(Board Plane)
V
CCPLL
(On i960
Jx processors)
0.01μF
4.7μF
+
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