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參數(shù)資料
| 型號： | 80960RN |
| 廠商： | Intel Corp. |
| 英文描述： | 80960RN I/O Processor(80960RN I/O 處理器) |
| 中文描述： | 80960RN I / O處理器（80960RN的I / O處理器） |
| 文件頁數(shù)： | 22/54頁 |
| 文件大?。?/td> | 851K |
| 代理商： | 80960RN |
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80960RN
—
Data Sheet
22
Advance Information
Table 7.
Secondary PCI Bus Signals (Sheet 1 of 2)
NAME
COUNT
TYPE
DESCRIPTION
S_AD[31:0]
32
I/O
5V
Sync(P)
Srst(0)
SECONDARY PCI ADDRESS/DATA
is the multiplexed secondary
PCI address and lower 32 bits of the data bus.
S_AD[63:32]
32
I/O
5V
Sync(P)
Srst(Z)
S32(H)
SECONDARY PCI DATA
is the upper 32 bits of the secondary PCI
data bus.
S_PAR
1
I/O
Sync(P)
Srst(0)
SECONDARY PCI BUS PARITY
is even parity across
S_AD[31:0]
and
S_C/BE[3:0]#
.
S_PAR64
1
I/O
5V
Sync(P)
Srst(Z)
S32(H)
SECONDARY PCI BUS UPPER DWORD PARITY
is even parity
across
S_AD[63:32]
and
S_C/BE[7:4]#
.
S_C/BE[3:0]#
4
I/O
5V
Sync(P)
Srst(0)
SECONDARY PCI BUS COMMAND and BYTE ENABLES
are
multiplexed on the same PCI pins. During the address phase, they
define the bus command. During the data phase, they are used as
the byte enables for
S_AD[31:0]
.
S_C/BE[7:4]#
4
I/O
5V
Sync(P)
Srst(Z)
S32(H)
SECONDARY PCI BYTE ENABLES
are used as byte enables for
S_AD[63:32]
during secondary PCI data phases.
S_REQ64#
1
I/O
5V
Sync(P)
Srst(Q)
S32(Z)
SECONDARY PCI BUS REQUEST 64-BIT TRANSFER
indicates
the attempt of a 64-bit transaction on the secondary PCI bus. If the
target is 64-bit capable, the target acknowledges the attempt with
the assertion of
S_ACK64#
.
S_ACK64#
1
I/O
5V
Sync(P)
Srst(Z)
S32(Z)
SECONDARY PCI BUS ACKNOWLEDGE 64-BIT TRANSFER
indicates that the device has positively decoded its address as the
target of the current access, indicates the target is willing to transfer
data using 64 bits.
S_FRAME#
1
I/O
5V
Sync(P)
Srst(Z)
SECONDARY PCI BUS CYCLE FRAME
is asserted to indicate the
beginning and duration of an access.
S_IRDY#
1
I/O
5V
Sync(P)
Srst(Z)
SECONDARY PCI BUS INITIATOR READY
indicates the initiating
agent
’
s ability to complete the current data phase of the
transaction. During a write, it indicates that valid data is present on
the secondary Address/Data bus. During a read, it indicates the
processor is ready to accept the data.
S_TRDY#
1
I/O
5V
Sync(P)
Srst(Z)
SECONDARY PCI BUS TARGET READY
indicates the target
agent
’
s ability to complete the current data phase of the
transaction. During a read, it indicates that valid data is present on
the secondary Address/Data bus. During a write, it indicates the
target is ready to accept the data.
S_STOP#
1
I/O
5V
Sync(P)
Srst(Z)
SECONDARY PCI BUS STOP
indicates a request to stop the
current transaction on the secondary PCI bus.
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