參數(shù)資料
型號(hào)： 82801E
廠商： INTEL CORP
元件分類： 外設(shè)及接口
英文描述： Intel 82801E Communications I/O Controller Hub (C-ICH)
中文描述： MULTIFUNCTION PERIPHERAL, PBGA421
封裝： BGA-421
文件頁(yè)數(shù)： 41/84頁(yè)
文件大小： 1196K
代理商： 82801E
Intel
82801E C-ICH
Advance Information Datasheet
41
3.2.7
LPC Interface
3.2.8
Interrupt Interface
Table 13. LPC Interface Signals
Name
Type
Description
LAD[3:0]
/FWH[3:0]
I/O
LPC Multiplexed Command, Address, Data:
Internal pull-ups are provided.
LFRAME#
/FWH[4]
O
LPC Frame:
LFRAME# indicates the start of an LPC cycle, or an abort.
LDRQ[1:0]#
I
LPC Serial DMA/Master Request Inputs:
These signals are used to request DMA or
bus master access. Typically, they are connected to external Super I/O device. An
internal pull-up resistor is provided on these signals.
Table 14. Interrupt Signals
Name
Type
Description
SERIRQ
I/O
Serial Interrupt Request:
This pin implements the serial interrupt protocol.
PIRQ[A:D]#
I/OD
PCI Interrupt Requests:
In Non-APIC Mode the PIRQx# signals can be routed
to interrupts 3:7, 9:12, 14, or 15 as described in the Interrupt Steering section.
Each PIRQx# line has a separate Route Control Register.
In APIC mode, these signals are connected to the internal I/O APIC in the
following fashion: PIRQ[A]# is connected to IRQ16, PIRQ[B]# to IRQ17,
PIRQ[C]# to IRQ18, and PIRQ[D]# to IRQ19. This frees the ISA interrupts.
PIRQ[E:F]#
PIRQ[G]#/GPIO[4]
PIRQ[H]#/GPIO[5]
I/OD
PCI Interrupt Requests:
In Non-APIC Mode the PIRQx# signals can be routed
to interrupts 3:7, 9:12, 14 or 15 as described in the Interrupt Steering section.
Each PIRQx# line has a separate Route Control Register.
In APIC mode, these signals are connected to the internal I/O APIC in the
following fashion: PIRQ[E]# is connected to IRQ20, PIRQ[F]# to IRQ21,
PIRQ[G]# to IRQ22, and PIRQ[H]# to IRQ23. This frees the ISA interrupts. If
not needed for interrupts, PIRQ[H:G] can be used as GPIO.
IRQ[14:15]
I
Interrupt Request 14:15:
These interrupt inputs are connected to the IDE
drives. IRQ14 is used by the drives connected to the primary controller and
IRQ15 is used by the drives connected to the secondary controller.
APICCLK
I
APIC Clock:
The APIC clock runs at 33.333 MHz.
APICD[1:0]
I/OD
APIC Data:
These bidirectional open drain signals are used to send and
receive data over the APIC bus. As inputs, the data is valid on the rising edge
of APICCLK. As outputs, new data is driven from the rising edge of the
APICCLK.
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