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參數(shù)資料
| 型號(hào)： | 82845GE |
| 廠商： | Intel Corp. |
| 英文描述： | 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH) |
| 中文描述： | 82845GE圖形和內(nèi)存控制器中樞（GMCH）和82845PE內(nèi)存控制器中樞（MCH） |
| 文件頁(yè)數(shù)： | 116/157頁(yè) |
| 文件大?。?/td> | 1407K |
| 代理商： | 82845GE |
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Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
116
Datasheet
250687-002
R
5.2.2.
Memory Organization and Configuration
Refer to Section 1.3.
5.2.2.1.
Configuration Mechanism for SO-DIMMs
Detection of the type of DDR installed on the SO-DIMM is supported via Serial Presence Detect
mechanism as defined in the JEDEC 200-pin SO- DIMM specification. This uses the SCL, SDA, and
SA[2:0] pins on the SO-DIMMs to detect the type and size of the installed SO-DIMMs. No special
programmable modes
are provided on Intel
845MP/845MZ MCH-M for detecting the size and type of
memory installed. Type and size detection must be done via the serial presence detection pins.
5.2.2.1.1.
Memory Detection and Initialization
Before any cycles to the memory interface can be supported, the Intel
845MP/845MZ MCH-M DDR
registers must be initialized. The Intel
845MP/845MZ MCH-M must be configured for operation with
the installed memory types. Detection of memory type and size is done via the System Management Bus
(SMB) interface on the ICH3-M. This two-wire bus is used to extract the DDR type and size information
from the Serial Presence Detect port on the DDR SO-DIMMs. DDR SO-DIMMs contain a 5 pin Serial
Presence Detect interface, including SCL (serial clock), SDA (serial data) and SA[2:0]. Devices on the
SMBus bus have a seven-bit address. For the DDR SO-DIMMs, the upper four bits are fixed at 1010.
The lower three bits are strapped on the SA[2:0] pins. SCL and SDA are connected directly to the
System Management Bus on the ICH3-M. Thus, data is read from the Serial Presence Detect port on the
SO-DIMMs via a series of IO cycles to the south bridge. BIOS essentially needs to determine the size
and type of memory used for each of the rows of memory in order to properly configure the Intel
845MP/845MZ MCH-M memory interface.
5.2.2.1.2.
SMBus Configuration and Access of the Serial Presence Detect Ports
Refer to the
Intel
ICH3-M Datasheet
for more detail.
5.2.2.1.3.
Memory Register Programming
This section provides an overview of how the required information for programming the DDR registers is
obtained from the Serial Presence Detect ports on the SO-DIMMs. The Serial Presence Detect ports are
used to determine Refresh Rate, MA and MD Buffer Strength, Row Type (on a row by row basis), DDR
Timings, Row Sizes, and Row Page Sizes. The following table lists a subset of the data available
through the onboard Serial Presence Detect ROM on each SO-DIMM.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 8284A | Clock Generator and Driver for 8066, 8088 Processors |
| 8284A-1 | Clock Generator and Driver for 8066, 8088 Processors |
| 8284 | TWO-OUTPUT LNB SUPPLY AND CONTROL-VOLTAGE REGULATOR |
| 82865G | Intel 865G/865GV Graphics and Memory Controller Hub |
| 82865GV | Intel 865G/865GV Graphics and Memory Controller Hub |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82845GL | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) |
| 82845GV | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) |
| 82845GX | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) |
| 82845MP | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
| 82845MX | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
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