參數(shù)資料
型號: 82845GE
廠商: Intel Corp.
英文描述: 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)
中文描述: 82845GE圖形和內(nèi)存控制器中樞(GMCH)和82845PE內(nèi)存控制器中樞(MCH)
文件頁數(shù): 143/157頁
文件大小: 1407K
代理商: 82845GE
9.4.
Intel
845MZ Chipset:82845MZ (MCH-M)
250687-001
Datasheet
143
R
Testability
In the
MCH-M
, testability for Automated Test Equipment (ATE) board level testing has been implemented
as and XOR chain. An XOR-tree is a chain of XOR gates, each with one input pin connected to it. Refer to
Figure 11 for an example XOR chain.
Figure 11. XOR–Tree Chain
Input
XOR
Out
xor.vsd
Input
Input
Input
Input
VCC1_8
The algorithm used for in –circuit test is as follows
Drive all input pins to an initial logic level ‘1’. Observe the output corresponding to scan chain being
tested.
Toggle pins one at a time starting from the first pin in the chain, continuing to the last pin, from its
initial logic level to the opposite logic level. Observe the output changes with each pin toggle.
9.4.1.
XOR Test Mode Initialization
XOR test mode can be entered by pulling three shared pins (reset straps) low through the rising transition
of RSTINB. The signals that need to be pulled are as follows:
GGNTB = 0 (Global strap enable)
SBA[1]
= 0 (XOR strap)
ST[2]
= 0 (PLL Bypass mode; it is recommended to enter PLL Bypass in XOR test mode)
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相關代理商/技術參數(shù)
參數(shù)描述
82845GL 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)
82845GV 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)
82845GX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)
82845MP 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
82845MX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)