參數(shù)資料
型號： 82845GE
廠商： Intel Corp.
英文描述： 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)
中文描述： 82845GE圖形和內(nèi)存控制器中樞（GMCH）和82845PE內(nèi)存控制器中樞（MCH）
文件頁數(shù)： 23/157頁
文件大?。?/td> 1407K
代理商： 82845GE
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
250687-002
Datasheet
23
R
2.2.
DDR Interface
Table 5. DDR Interface Signal Descriptions
Signal Name
Type
Description
SCS#[3:0]
O
CMOS
Chip Select:
These pins select the particular DDR components during the active
state.
Note:
There is one SCS# per DDR-SDRAM Physical SO-DIMM device row. These
signals can be toggled on every rising System Memory Clock edge.
SMA[12:0]
O
CMOS
Multiplexed Memory Address:
These signals are used to provide the multiplexed
row and column address to DDR.
SBS[1:0]
O
CMOS
Memory Bank Address:
These signals define the banks that are selected within
each DDR row. The SMA and SBS signals combine to address every possible
location within a DDR device.
SRAS#
O
CMOS
DDR Row Address Strobe:
SRAS# may be heavily loaded and requires 2 DDR
clock cycles for setup time to the DDRs:
Used with SCAS# and SWE# (along with
SCS#) to define the DRAM commands.
SCAS#
O
CMOS
DDR Column Address Strobe:
SCAS# may be heavily loaded and requires 2 DDR
clock cycles for setup time to the DDRs. Used with SRAS# and SWE# (along with
SCS#) to define the DRAM commands.
SWE#
I/O
CMOS
Write Enable:
Used with SCAS# and SRAS# (along with SCS#) to define the
DRAM commands. SWE# is asserted during writes to DDR. SWE# may be heavily
loaded and requires 2 DDR clock cycles for setup time to the DDRs.
SDQ[63:0]
I/O
CMOS 2X
Data Lines:
These signals are used to interface to the DDR data bus.
SCB[7:0]
I/O
CMOS 2X
Data Lines:
These signals are used to interface to the SDRAM ECC signals (to be
used if SO-DIMMs support ECC).
SDQS[8:0]
I/O
CMOS
Data Strobes:
There is an associated data strobe (DQS) for each data strobe (DQ) and check
bit (CB) group.
SDQS8
-
> SCB[7:0]
SDQS7 -> SDQ[63:56]
SDQS6 -> SDQ[55:48]
SDQS5 -> SDQ[47:40]
SDQS4 -> SDQ[39:32]
SDQS3 -> SDQ[31:24]
SDQS2 -> SDQ[23:16]
SDQS1 -> SDQ[15:8]
SDQS0 -> SDQ[7:0]
SCKE[3:0]
O
CMOS
Clock Enable:
These pins are used to signal a self-refresh or power down
command to a DDR array when entering system suspend. SCKE is also used to
dynamically power down inactive DDR rows. There is one SCKE per DDR row.
These signals can be toggled on every rising SCLK edge.
RCVENOUT#
O
CMOS
Clock Output:
Used to emulate source-synch clocking for reads. Connects to
RCVENIN#.
RCVENIN#
I
CMOS
Clock Input:
Used to emulate source-synch clocking for reads. Connects to
RCVENOUT#.
相關(guān)PDF資料
PDF描述
8284A Clock Generator and Driver for 8066, 8088 Processors
8284A-1 Clock Generator and Driver for 8066, 8088 Processors
8284 TWO-OUTPUT LNB SUPPLY AND CONTROL-VOLTAGE REGULATOR
82865G Intel 865G/865GV Graphics and Memory Controller Hub
82865GV Intel 865G/865GV Graphics and Memory Controller Hub
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
82845GL 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)
82845GV 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)
82845GX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)
82845MP 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
82845MX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*