參數(shù)資料
型號: 82C862
廠商: Electronic Theatre Controls, Inc.
英文描述: FireLink USB Dual Controller Quad Port USB
中文描述: FireLink雙控制器的USB四口USB
文件頁數(shù): 12/51頁
文件大小: 321K
代理商: 82C862
FireLink USB
82C862
912-2000-030
Revision: 1.0
Page 8
DEVSEL#
69
I/O
(s/t/s)
Device Select:
The 82C862 claims a PCI cycle via positive decoding by
asserting DEVSEL#. As an output, the 82C862 drives DEVSEL# for two different
reasons:
1.
If the 82C862 samples IDSEL active in configuration cycles, DEVSEL# is
asserted.
2.
decodes a cycle, DEVSEL# is asserted
When the 82C862 decodes an internal address or when it subtractively
When DEVSEL# is an input, it indicates the target response to an 82C862
master-initiated cycle. DEVSEL# is tristated from the leading edge of RESET#
and remains so until driven by the 82C862 acting as a slave.
IDSEL
50
I
Initialization Device Select:
This signal is the "chip select" during configuration
read and write cycles. IDSEL is sampled by the 82C862 during the address
phase of a cycle. If IDSEL is found to be active and the bus command is a
configuration read or write, the 82C862 claims the cycle with DEVSEL#.
PERR#
71
I/O
Parity Error:
The 82C862 uses this line to report data parity errors during any
PCI cycle except a Special Cycle.
SERR#
75
I
System Error:
The 82C862 uses this line to report address parity errors and data
parity errors on the Special Cycle command, or any other system error where the
result will be catastrophic.
REQ#
36
O
Bus Request:
REQ# is asserted by the 82C862 to request ownership of the PCI
bus.
GNT#
35
I
Bus Grant:
GNT# is sampled by the 82C862 for an active low assertion, which
indicates that it has been granted use of the PCI bus.
CLKRUN#
46
I/O
Clock Run:
The CLKRUN# function is available on this pin and can be used to
reduce chip power consumption during idle periods. It is an I/O sustained tristate
signal and follows the PCI 2.1 defined protocol.
GPIO2
General Purpose I/O pin 2:
These pins can be written or read by specific
application software. Refer to PCICFG 53-55h for information.
3.3.3 USB Interface Signals
Signal Name
Pin
No.
Pin
Type
Signal Description
D1+/D1-
13/14
diff
USB Port 1 Differential Data Pair:
This pair comes from the first controller.
D2+/D2-
15/16
diff
USB Port 2 Differential Data Pair:
This pair comes from the first controller.
D3+/D3-
28/29
diff
USB Port 3 Differential Data Pair:
This pair comes from the second controller.
D4+/D4-
30/31
diff
USB Port 4 Differential Data Pair:
This pair comes from the second controller.
PWRON1#
PWRON2#
PWRON3#
PWRON4#
53
24
73
90
O
Power On Lines 1, 2, 3 and 4:
These outputs are used to switch port VCC for
the respective USB port. The controlled VCC is used only by the device
connected to the port, and is not used by the 82C862 controller.
PWRFLT1#
PWRFLT2#
PWRFLT3#
PWRFLT4#
54
23
74
91
I
Power Fault Lines 1, 2, 3 and 4:
These inputs indicate that an over-current fault
has occurred on the respective USB port. Their polarity can be both strap- and
software-controlled: Refer to the Strap Options section for details.
相關PDF資料
PDF描述
82C931 Plug and Play Integrated Audio Controller
82S09 576-BIT BIPOLAR RAM (64 X 9)
82S19 576-BIT BIPOLAR RAM (64 X 9)
82S101BYA 2.6GHz Relay, 1 Form C, 0.5A 30VDC Relay, 50ohms, SMD
82S100BXA 1 MSPS, 12-Bit A/D Converter in MSOP-8 or SOIC-8; Package: MSOP; No of Pins: 8; Temperature Range: Industrial
相關代理商/技術參數(shù)
參數(shù)描述
82C86H 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Octal Bus Transceiver
82C86H_04 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Octal Bus Transceiver
82C87 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Octal Inverting Bus Transceiver
82C871(100LQFP) 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER
82C871(100QFP) 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER