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參數(shù)資料
| 型號(hào)： | 82C862 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | FireLink USB Dual Controller Quad Port USB |
| 中文描述： | FireLink雙控制器的USB四口USB |
| 文件頁數(shù)： | 13/51頁 |
| 文件大?。?/td> | 321K |
| 代理商： | 82C862 |
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FireLink USB
82C862
912-2000-030
Revision 1.0
Page 9
3.3.4 Host Controller shared signals: PME#, SMI#, REQ#, GNT#
Several other signals are shared by both host controllers in addition to the bused PCI signals. The shared signals are all active
low. The diagram below best explains the internal connections of the 82C862 device.
3.3.5 Legacy and Interrupt Interface Signals
Signal Name
Pin
No.
Pin
Type
Signal Description
SMI#
97
O
System Management Interrupt:
This signal is used to request a System
Management Mode (SMM) interrupt. It can be connected to a spare EPMI pin on
the host chipset.
GPIO4
General Purpose I/O pin 4:
These pins can be written or read by specific
application software. Refer to PCICFG 53-55h for information.
PME#
72
special
Power Management Event:
This signal is used to wake up the system from a
PCI Power Management (PCI/PM) power saving mode. This pin is normally tri-
stated and is driven low when active.
Note:
When unpowered, the PME# driver output circuit will not be damaged if
PME# is powered from another source. Moreover, once power is removed from
the chip, this pin does not present a current path to ground.
GPIO3
General Purpose I/O pin 3:
These pins can be written or read by specific
application software. Refer to PCICFG 53-55h for information.
INTA#
1
O
PCI Interrupt A:
This signal can be connected to a PCI interrupt line.
TEST0
21
I/O
TEST Pin 0:
This pin is sampled by the chip at reset time to put the logic into a
test mode if needed. See the STRAP OPTIONS section for details.
GPIO0
General Purpose I/O pin 0:
These pins can be written or read by specific
application software. Refer to PCICFG 53-55h for information.
TEST1
25
I/O
TEST Pin 1:
This pin is sampled by the chip at reset time to put the logic into a
test mode if needed. See the STRAP OPTIONS section for details.
GPIO1
General Purpose I/O pin 1:
These pins can be written or read by specific
application software. Refer to PCICFG 53-55h for information.
SMI2#
PME2#
Internal
Arbiter
PME#
SMI
#
REQ#
GNT#
REQ1#
SMI1#
PME1#
FireLink USB
GNT1#
USB
Host1
GNT2#
USB
Host2
REQ2#
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