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參數(shù)資料
| 型號(hào)： | 82C862 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | FireLink USB Dual Controller Quad Port USB |
| 中文描述： | FireLink雙控制器的USB四口USB |
| 文件頁(yè)數(shù)： | 34/51頁(yè) |
| 文件大?。?/td> | 321K |
| 代理商： | 82C862 |
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FireLink USB
82C862
912-2000-030
Revision: 1.0
Page 30
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MEMOFST 08h
HcCommandStatus Register - Byte 0
Default = 00h
Reserved
Ownership
Change
Request:
When set by
software, this
bit sets the
Ownership
Change bit
(MEMOFST
0Fh[6]).
Cleared by
software.
Bulk List has
an active
endpoint
descriptor(1)
0 = No
1 = Yes
Control List
has an active
endpoint
descriptor(1)
0 = No
1 = Yes
HC Reset:
Writing a 1
initiates a
software reset.
This bit is
cleared by the
HC upon
completion of
reset operation.
(1) The bit may be set by either software or the HC. It is cleared by the HC each time it begins processing the head of the list (Bulk List for
bit 2, Control List for bit 1)
MEMOFST 09h
HcCommandStatus Register - Byte 1
Default = 00h
Reserved
MEMOFST 0Ah
HcCommandStatus Register - Byte 2
Default = 00h
Reserved
Schedule Overrun Count:
This field increments every time
the Scheduling Overrun bit
(MEMOFST 0Ch[0] is set. The
count wraps from 11 to 00.
MEMOFST 0Bh
HcCommandStatus Register - Byte 3
Default = 00h
Reserved
MEMOFST 0Ch
HcInterrupt Status Register - Byte 0*
Default = 00h
Reserved
Root Hub
Status
Change:
This bit is set
when the
content of HcRh
Status (50h-
53h) or the
content of any
HcRhPort
Status Register
(54h-5Bh) has
changed.
Frame Number
Overflow:
This bit is set
when
MEMOFST
3Ch[15] (Frame
Number
Register)
changes from
0-to-1 or from
1-to-0.
Unrecoverable
Error:
This event is
not
implemented
and is
hardcoded to 0.
All writes are
ignored.
Resume
Detected:
This bit is set
when the HC
detects resume
signaling on a
downstream
port.
Start of Frame:
This bit is set
when the
Frame
Management
block signals a
"Start of Frame"
event.
Writeback
Done Head:
This bit is set
after the Host
Controller has
written
HcDoneHead to
HccaDoneHead
.
Scheduling
Overrun
occurred
0 = No
1 = Yes
MEMOFST 0Dh-0Eh
HcInterruptStatus Register - Bytes 1 & 2
Default = 00h
Reserved
MEMOFST 0Fh
HcInterruptStatus Register - Byte 3*
Default = 00h
Reserved
Ownership
Change:
This bit is set
when the
Ownership
Change
Request bit
(MEMOFST
08h[3]) is set.
Reserved
* Writing a 1 to a bit in this register clears the corresponding bit, while writing a 0 leaves the bit unchanged.
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